Semiconductor device and manufacturing method thereof

ABSTRACT

A transistor with favorable electrical characteristics is provided. A minute transistor is provided. Provided is a semiconductor device including a first insulator over a substrate, a second insulator over the first insulator, a semiconductor over the second insulator, a first conductor and a second conductor over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor, and the second conductor. In the semiconductor device, the second insulator and the third insulator each include at least one element other than oxygen included in the semiconductor, respectively, and the semiconductor includes a region having a carbon concentration of 3×10 18  atoms/cm 3  or lower.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to, for example, a transistor, a semiconductor device, and manufacturing methods thereof. The present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, and an electronic device. The present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, an imaging device, and an electronic device. The present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.

2. Description of the Related Art

In recent years, a transistor including an oxide semiconductor has attracted attention. It is known that a transistor including an oxide semiconductor has an extremely low leakage current in an off state. For example, a low-power-consumption CPU utilizing a characteristic of low leakage current of the transistor including an oxide semiconductor is disclosed (see Patent Document 1).

A method for manufacturing a transistor including an oxide semiconductor by forming a gate electrode so as to fill an opening is disclosed (see Patent Documents 2 and 3).

REFERENCE Patent Document [Patent Document 1] Japanese Published Patent Application No. 2012-257187 [Patent Document 2] Japanese Published Patent Application No. 2014-241407 [Patent Document 3] Japanese Published Patent Application No. 2014-240833 SUMMARY OF THE INVENTION

An object is to provide a minute transistor. Another object is to provide a transistor with low parasitic capacitance. Another object is to provide a transistor with high frequency characteristics. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor with low off-state current. Another object is to provide a novel transistor. Another object is to provide a semiconductor device including the above transistor. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a novel semiconductor device. Another object is to provide a module including the above semiconductor device. Another object is to provide an electronic device including the above semiconductor device or the above module.

Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all of the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

One embodiment of the present invention is a semiconductor device including a first insulator over a substrate, a second insulator over the first insulator, a semiconductor over the second insulator, a first conductor and a second conductor over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor, and the second conductor. In the semiconductor device, the second insulator and the third insulator each include at least one element other than oxygen included in the semiconductor, and the semiconductor includes a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower.

In the semiconductor device of one embodiment of the present invention, the third insulator has a stacked structure including two or more layers.

In the semiconductor device of one embodiment of the present invention, the first conductor, the second conductor, and the third conductor each have a stacked structure including two or more layers.

The semiconductor device of one embodiment of the present invention further includes a fourth conductor between the substrate and the first insulator.

In the semiconductor device of one embodiment of the present invention, the second insulator includes a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower.

In the semiconductor device of one embodiment of the present invention, the third insulator includes a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower.

In the semiconductor device of one embodiment of the present invention, the semiconductor includes a CAAC-OS.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: performing high-density plasma treatment after a first insulator is formed; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; processing part of the second insulator and part of the semiconductor to form a multilayer film including the second insulator and the semiconductor; forming a first conductor over the multilayer film; processing part of the first conductor to form a second conductor; forming a third insulator over the second conductor and the first insulator; forming an opening through which the semiconductor and the first insulator are exposed, in the third insulator and the second conductor to divide the second conductor into a third conductor and a fourth conductor; forming a fourth insulator over the third insulator, the third conductor, the fourth conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; and forming a fifth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulator; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; performing high-density plasma treatment after part of the second insulator and part of the semiconductor are processed to form a multilayer film including the second insulator and the semiconductor; forming a first conductor over the multilayer film; processing part of the first conductor to form a second conductor; forming a third insulator over the second conductor and the first insulator; forming an opening through which the semiconductor and the first insulator are exposed, in the third insulator and the second conductor to divide the second conductor into a third conductor and a fourth conductor; forming a fourth insulator over the third insulator, the third conductor, the fourth conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; and forming a fifth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulator; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; processing part of the second insulator and part of the semiconductor to form a multilayer film including the second insulator and the semiconductor; forming a first conductor over the multilayer film; processing part of the first conductor to form a second conductor; forming a third insulator over the second conductor and the first insulator; performing high-density plasma treatment after an opening through which the semiconductor and the first insulator are exposed is formed in the third insulator and the second conductor to divide the second conductor into a third conductor and a fourth conductor; forming a fourth insulator over the third insulator, the third conductor, the fourth conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; and forming a fifth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulator; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; processing part of the second insulator and part of the semiconductor to form a multilayer film including the second insulator and the semiconductor; forming a first conductor over the multilayer film; processing part of the first conductor to form a second conductor; forming a third insulator over the second conductor and the first insulator; forming an opening through which the semiconductor and the first insulator are exposed, in the third insulator and the second conductor to divide the second conductor into a third conductor and a fourth conductor; performing high-density plasma treatment after a fourth insulator is formed over the third insulator, the third conductor, the fourth conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; and forming a fifth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulator; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; processing part of the second insulator and part of the semiconductor to form a multilayer film including the second insulator and the semiconductor; forming a first conductor over the multilayer film; processing part of the first conductor to form a second conductor; forming a third insulator over the second conductor and the first insulator; forming a first opening through which the semiconductor and the first insulator are exposed, in the third insulator and the second conductor to divide the second conductor into a third conductor and a fourth conductor; forming a fourth insulator over the third insulator, the third conductor, the fourth conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; forming a fifth conductor over the fifth insulator, processing the fifth conductor to form a sixth conductor; and performing high-density plasma treatment after the third insulator is processed to form a second opening and a third opening through which part of the third conductor and part of the fourth conductor are exposed. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: performing high-density plasma treatment after a first insulator is formed; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; forming a first conductor over the semiconductor; processing part of the second insulator, part of the semiconductor, and part of the first conductor to form a multilayer film including the second insulator, the semiconductor, and the first conductor; forming a third insulator over the multilayer film; forming an opening through the semiconductor is exposed, in the third insulator and the first conductor to divide the first conductor into a second conductor and a third conductor; forming a fourth insulator over the third insulator, the second conductor, the third conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; and forming a fourth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulator; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; forming a first conductor over the semiconductor; processing part of the second insulator, part of the semiconductor, and part of the first conductor to form a multilayer film including the second insulator, the semiconductor, and the first conductor; forming a third insulator over the multilayer film; performing high-density plasma treatment after an opening through which the semiconductor is exposed is formed in the third insulator and the first conductor to divide the first conductor into a second conductor and a third conductor; forming a fourth insulator over the third insulator, the second conductor, the third conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; and forming a fourth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming a first insulator; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; forming a first conductor over the semiconductor; processing part of the second insulator, part of the semiconductor, and part of the first conductor to form a multilayer film including the second insulator, the semiconductor, and the first conductor; forming a third insulator over the multilayer film; forming an opening through which the semiconductor is exposed, in the third insulator and the first conductor to divide the first conductor into a second conductor and a third conductor; forming a fourth insulator over the third insulator, the second conductor, the third conductor, and the semiconductor; performing high-density plasma treatment after a fifth insulator is formed over the fourth insulator; and forming a fourth conductor over the fifth insulator. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: performing high-density plasma treatment after a first insulator is formed; forming a second insulator over the first insulator; forming a semiconductor over the second insulator; forming a first conductor over the semiconductor; processing part of the second insulator, part of the semiconductor, and part of the first conductor to form a multilayer film including the second insulator, the semiconductor, and the first conductor; forming a third insulator over the multilayer film; forming a first opening through which the semiconductor is exposed, in the third insulator and the first conductor to divide the first conductor into a second conductor and a third conductor; forming a fourth insulator over the third insulator, the second conductor, the third conductor, and the semiconductor; forming a fifth insulator over the fourth insulator; forming a fourth conductor over the fifth insulator; processing the fourth conductor to form a fifth conductor; and performing high-density plasma treatment after the third insulator is processed to form a second opening and a third opening through which part of the second conductor and part of the third conductor are exposed. The second insulator and the fourth insulator each include at least one element other than oxygen included in the semiconductor.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, the high-density plasma treatment is performed with a high-frequency generator that generates a wave having a frequency of more than or equal to 0.3 GHz and less than or equal to 3.0 GHz.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, the high-density plasma treatment is performed in an oxygen atmosphere.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, the high-density plasma treatment is performed in a nitrogen atmosphere.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, the high-density plasma treatment is performed while a substrate bias is applied.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, annealing treatment is performed following the high-density plasma treatment.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, the high-density plasma treatment is performed following annealing treatment.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, at least one of the first insulator and the third insulator is formed using a tetraethoxysilane (TEOS; chemical formula: Si(OC₂H₅)₄) gas.

A minute transistor can be provided. A transistor with low parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A transistor with favorable electrical characteristics can be provided. A transistor with stable electrical characteristics can be provided. A transistor with low off-state current can be provided. A novel transistor can be provided. A semiconductor device including the above transistor can be provided. A semiconductor device that operates at high speed can be provided. A novel semiconductor device can be provided. A module including the above semiconductor device can be provided. An electronic device including the above semiconductor device or the above module can be provided.

Note that the descriptions of these effects do not disturb the existence of other effects. One embodiment of the present invention does not necessarily have all of the effects. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1C are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention;

FIGS. 2A to 2C are a top view and cross-sectional views which illustrate a transistor of one embodiment of the present invention;

FIGS. 3A and 3B are cross-sectional views each illustrating part of a transistor of one embodiment of the present invention;

FIG. 4 is a band diagram according to one embodiment of the present invention;

FIGS. 5A to 5D are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS;

FIGS. 6A to 6D are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS;

FIGS. 7A to 7C show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD;

FIGS. 8A and 8B show electron diffraction patterns of a CAAC-OS;

FIG. 9 shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation;

FIGS. 10A to 10C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 11A to 11C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 12A to 12C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 13A to 13C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 14A to 14C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 15A to 15C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 16A to 16C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 17A to 17C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 18A to 18C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 19A to 19C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 20A to 20C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 21A to 21C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 22A to 22C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 23A to 23C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 24A to 24C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 25A to 25C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 26A to 26C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 27A to 27C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIGS. 28A to 28C are a top view and cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention;

FIG. 29 is a top view illustrating a manufacturing apparatus according to one embodiment of the present invention;

FIG. 30 is a cross-sectional view illustrating a chamber according to one embodiment of the present invention;

FIG. 31 is a cross-sectional view illustrating a chamber according to one embodiment of the present invention;

FIGS. 32A and 32B are circuit diagrams each illustrating a memory device of one embodiment of the present invention;

FIG. 33 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention;

FIG. 34 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention;

FIGS. 35A to 35F are circuit diagrams and cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention;

FIG. 36 is a block diagram illustrating a CPU according to one embodiment of the present invention;

FIG. 37 is a circuit diagram of a memory element according to one embodiment of the present invention;

FIGS. 38A and 38B are plan views each illustrating an imaging device;

FIGS. 39A and 39B are plan views illustrating pixels of an imaging device;

FIGS. 40A and 40B are cross-sectional views each illustrating an imaging device;

FIGS. 41A and 41B are cross-sectional views each illustrating an imaging device;

FIG. 42 illustrates a configuration example of an RF tag;

FIGS. 43A to 43C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

FIGS. 44A and 44B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

FIG. 45 illustrates a display module;

FIG. 46A is a perspective view illustrating a cross-sectional structure of a package using a lead frame interposer, and FIG. 46B is a top view illustrating a structure of a module of an electronic device in which a package is mounted on a circuit board;

FIGS. 47A to 47E each illustrate an electronic device according to one embodiment of the present invention;

FIGS. 48A to 48D each illustrate an electronic device according to one embodiment of the present invention;

FIGS. 49A to 49C each illustrate an electronic device according to one embodiment of the present invention;

FIGS. 50A to 50F illustrate application examples of an RF tag according to one embodiment of the present invention;

FIG. 51 shows the concentration of carbon in the depth direction;

FIG. 52 shows TDS results; and

FIGS. 53A and 53B show HX-PES analysis results.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiment of the present invention will be described in detail with the reference to the drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways. Further, the present invention is not construed as being limited to description of the following embodiments. In describing structures of the present invention with reference to the drawings, common reference numerals are used for the same portions in different drawings. Note that the same hatched pattern is applied to similar parts, and the similar parts are not especially denoted by reference numerals in some cases.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

In this specification, for example, when the shape of an object is described with the use of a term such as “diameter”, “grain size (diameter)”, “dimension”, “size”, or “width”, the term can be regarded as the length of one side of a minimal cube where the object fits, or an equivalent circle diameter of a cross section of the object. The term “equivalent circle diameter of a cross section of the object” refers to the diameter of a perfect circle having the same area as that of the cross section of the object.

A voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a ground potential (GND) or a source potential). A voltage can be referred to as a potential and vice versa.

Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those which specify one embodiment of the present invention.

Note that an impurity in a semiconductor refers to, for example, elements other than main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % is an impurity. When an impurity is contained, the density of states (DOS) may be formed in a semiconductor, the carrier mobility may be decreased, or the crystallinity may be decreased, for example. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen. Further, in the case where the semiconductor is a silicon film, examples of the impurity which changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

Note that the channel length refers to, for example, a distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is high in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.

In a transistor having a three-dimensional structure, the effective channel width is difficult to measure in some cases. For example, estimation of the effective channel width from a design value requires an assumption that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure the effective channel width accurately.

Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.

Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values may be different from those calculated using an effective channel width.

Note that in this specification, the description “A has a shape such that an end portion extends beyond an end portion of B” may indicate, for example, the case where at least one of end portions of A is positioned on an outer side of at least one of end portions of B in a top view or a cross-sectional view. Thus, the description “A has a shape such that an end portion extends beyond an end portion of B” can be read as the description “one end portion of A is positioned on an outer side of one end portion of B in a top view,” for example.

In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.

In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

In this specification, a term “semiconductor” can be referred to as an “oxide semiconductor”. As the semiconductor, a Group 14 semiconductor such as silicon or germanium; a compound semiconductor such as silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, or cadmium sulfide; a carbon nanotube; graphene; or an organic semiconductor can be used.

Note that in this specification and the like, a “silicon oxynitride film” refers to a film that includes oxygen at a higher proportion than nitrogen, and a “silicon nitride oxide film” refers to a film that includes nitrogen at a higher proportion than oxygen.

Note that in the case where at least one specific example is described in a diagram or text described in one embodiment in this specification and the like, it will be readily appreciated by those skilled in the art that a broader concept of the specific example can be derived. Therefore, in the diagram or the text described in one embodiment, in the case where at least one specific example is described, a broader concept of the specific example is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. The embodiment of the present invention is clear.

Note that in this specification and the like, a content described in at least a diagram (or may be part of the diagram) is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Therefore, when a certain content is described in a diagram, the content is disclosed as one embodiment of the invention even when the content is not described with a text, and one embodiment of the invention can be constituted. Similarly, part of a diagram, which is taken out from the diagram, is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. The embodiment of the present invention is clear.

In addition, contents that are not specified in any text or drawing in the specification can be excluded from one embodiment of the invention. Alternatively, when the range of a value that is defined by the maximum and minimum values is described, part of the range is appropriately narrowed or part of the range is removed, whereby one embodiment of the invention excluding part of the range can be constituted. In this manner, it is possible to specify the technical scope of one embodiment of the present invention so that a conventional technology is excluded, for example.

Embodiment 1 Transistor Structure 1

A structure of a transistor included in a semiconductor device of one embodiment of the present invention is described below.

FIGS. 1A to 1C are a top view and cross-sectional views of the semiconductor device of one embodiment of the present invention. FIG. 1A is the top view. FIG. 1B is the cross-sectional view taken along a dashed-dotted line A1-A2 in FIG. 1A and illustrates a cross-sectional shape in a channel length direction. FIG. 1C is the cross-sectional view taken along a dashed-dotted line A3-A4 in FIG. 1A and illustrates a cross-sectional shape in a channel width direction. Note that in the top view of FIG. 1A, some components are not illustrated for simplification of the drawing.

A transistor illustrated in FIGS. 1A to 1C includes a conductor 413 over a substrate 400, an insulator 402 over the conductor 413, an insulator 406 a over the insulator 402, a semiconductor 406 b over the insulator 406 a, a conductor 416 a 1 and a conductor 416 a 2 each having a region in contact with the semiconductor 406 b, an insulator 410 in contact with top surfaces of the conductor 416 a 1 and the conductor 416 a 2, an insulator 406 c in contact with top and side surfaces of the semiconductor 406 b, an insulator 412 over the insulator 406 c, a conductor 404 positioned over the semiconductor 406 b with the insulator 412 and the insulator 406 c interposed therebetween, openings reaching the conductor 416 a 1 and the conductor 416 a 2 through the insulator 410, a conductor 417 a 1 and a conductor 417 a 2 embedded in the openings, a conductor 418 a 1 over the conductor 417 a 1, a conductor 418 a 2 over the conductor 417 a 2, and a conductor 418 a 3 over the conductor 404.

The insulator 406 a and the insulator 406 c preferably include at least one element other than oxygen included in the semiconductor 406 b. This can suppress generation of defects at an interface between the semiconductor 406 b and the insulator 406 a and an interface between the semiconductor 406 b and the insulator 406 c.

The insulator 406 a, the semiconductor 406 b, and the insulator 406 c preferably include a CAAC-OS which is described later. The insulator 406 a, the semiconductor 406 b, and the insulator 406 c each preferably include a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower; in this way, the insulator 406 a, the semiconductor 406 b, and the insulator 406 c can have higher crystallinity. As a method for obtaining a carbon concentration of 3×10¹⁸ atoms/cm³ or lower, high-density plasma treatment is preferably performed. In particular, by performing high-density plasma treatment in an oxygen atmosphere, it is not only possible to reduce the carbon concentration but also to add oxygen. Thus, oxygen vacancies in the semiconductor 406 b can be filled.

The semiconductor 406 b preferably includes a region having a nitrogen concentration of higher than or equal to 0.001 at % and lower than or equal to 3 at %. In this way, oxygen vacancies can be immobilized and a stable transistor can be manufactured. As a method for obtaining a nitrogen concentration of higher than or equal to 0.001 at % and lower than or equal to 3 at %, high-density plasma treatment is preferably performed.

Furthermore, the insulator 402, the insulator 410, and the insulator 412 each preferably include a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower. In this way, the insulator 402, the insulator 410, and the insulator 412 can have higher withstand voltages and leakage current can be reduced. As a method for obtaining a carbon concentration of 3×10¹⁸ atoms/cm³ or lower, high-density plasma treatment is preferably performed. In particular, high-density plasma treatment in an oxygen atmosphere enables not only a reduction of the carbon concentration but also an addition of oxygen. Following the high-density plasma treatment in an oxygen atmosphere, high-density plasma treatment in a nitrogen atmosphere may be performed.

In this transistor, the conductor 404 functions as a first gate electrode. The conductor 404 can have a stacked structure including a conductor that does not easily transmit oxygen. For example, when the conductor that does not easily transmit oxygen is formed as a lower layer, a decrease in conductivity caused by oxidation of the conductor 404 can be prevented. The insulator 412 functions as a first gate insulator. Note that the conductivity of the conductor can be measured by a two-terminal method or the like.

The conductor 413 functions as a second gate electrode. The conductor 413 can have a stacked structure including a conductive film that does not easily transmit oxygen. When the conductor 413 has a stacked structure including a conductive film that does not easily transmit oxygen, a decrease in conductivity caused by oxidation of the conductor 413 can be prevented. The insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by a potential applied to the conductor 413. Furthermore, when the first gate electrode and the second gate electrode are electrically connected to each other, a high on-state current can be obtained. Note that the function of the first gate electrode may be interchanged with the function of the second gate electrode.

FIGS. 2A to 2C illustrate an example in which the first gate electrode and the second gate electrode are electrically connected to each other. By providing an opening in the insulator 402 and the insulator 410 as illustrated in FIG. 2C, the conductor 413 and the conductor 404 are electrically connected to each other.

The conductor 416 a 1 and the conductor 416 a 2 function as a source and drain electrodes. The conductor 416 a 1 and the conductor 416 a 2 each preferably have regions having different thicknesses. For example, the conductor 416 a 1 and the conductor 416 a 2 each preferably have a small thickness in a region in contact with the insulator 406 c. The conductor 416 a 1 and the conductor 416 a 2 can have a stacked structure including a conductor that does not easily transmit oxygen. For example, when the conductor that does not easily transmit oxygen is formed as an upper layer, a decrease in conductivity caused by oxidation of the conductor 416 a 1 and the conductor 416 a 2 can be prevented.

The resistance of the semiconductor 406 b can be controlled by a potential applied to the conductor 404. That is, conduction or non-conduction between the conductors 416 a 1 and 416 a 2 can be controlled by the potential applied to the conductor 404.

As illustrated in FIG. 1B, the top surface of the semiconductor 406 b is in contact with the conductors 416 a 1 and 416 a 2. In addition, the semiconductor 406 b can be electrically surrounded by an electric field of the conductor 404 functioning as the gate electrode. A structure in which a semiconductor is electrically surrounded by an electric field of a gate electrode is referred to as a surrounded channel (s-channel) structure. Thus, in some cases, a channel is formed in the entire semiconductor 406 b. In the s-channel structure, a large amount of current can flow between a source and a drain of the transistor, so that an on-state current can be increased. In addition, since the semiconductor 406 b is surrounded by the electric field of the conductor 404, an off-state current can be decreased.

In the transistor of this embodiment, the region functioning as a gate electrode is formed in a self-aligned manner by filling an opening formed in the insulator 410 and the like; thus, this transistor may be called a trench gate self-aligned (TGSA) s-channel FET.

Furthermore, a structure without the conductor 413 may also be employed (see FIG. 3A). The conductor 404 may have a shape as illustrated in FIG. 3B. This shape can be formed by a photolithography method, for example. A transistor illustrated in FIG. 3B includes an insulator 420 over the conductor 404 and the insulator 410, the conductor 417 a 1 and the conductor 417 a 2 which fill openings provided in the insulator 410 and the insulator 420, the conductor 418 a 1 and the conductor 418 a 2 which are connected to the conductor 417 a 1 and the conductor 417 a 2, respectively, the conductor 417 a 3 which fills an opening provided in the insulator 420, and the conductor 418 a 3 which is connected to the conductor 417 a 3.

The insulator 406 a, the semiconductor 406 b, and the insulator 406 c may each have a stacked structure including two or more layers.

As the substrate 400, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a single material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide is used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like may be used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like can be used. A substrate including a metal nitride, a substrate including a metal oxide, or the like may be used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like may be used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. As a method for providing the transistor over a flexible substrate, there is a method in which the transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to the substrate 400 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate 400, a sheet, a film, a foil, or the like containing fiber may be used. The substrate 400 may have elasticity. The substrate 400 may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 400 may have a property of not returning to its original shape. The substrate 400 has a region with a thickness of, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, further preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate 400 has a small thickness, the weight of the semiconductor device including the transistor can be reduced. When the substrate 400 has a small thickness, even in the case of using glass or the like, the substrate 400 may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 400, which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided.

As a flexible substrate used as the substrate 400, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate used as the substrate 400 preferably has as low a coefficient of linear expansion as possible in order to suppress deformation due to the environment. The flexible substrate used as the substrate 400 is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10⁻³/K, lower than or equal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used as the flexible substrate used as the substrate 400 because of its low coefficient of linear expansion.

When the transistor is surrounded by an insulator which has a function of blocking oxygen and impurities such as hydrogen, stable electrical characteristics of the transistor can be obtained. For example, an insulator 401, the insulator 402, the insulator 412, or the insulator 410 may include a single layer or stacked layers of an insulator which has a function of blocking oxygen and impurities such as hydrogen.

The insulator which has a function of blocking oxygen and impurities such as hydrogen may include a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

Alternatively, as the insulator which has a function of blocking oxygen and impurities such as hydrogen, aluminum oxide, magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used. for example,

The insulator 402 may include a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator 402 preferably includes silicon oxide or silicon oxynitride.

The insulator 410 preferably includes an insulator with a low relative dielectric constant. For example, the insulator 410 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, the insulator 410 preferably has a stacked structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked structure can have thermal stability and a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

The insulator 412 may include a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator 412 preferably includes silicon oxide or silicon oxynitride.

Note that the insulator 412 preferably includes an insulator with a high relative dielectric constant. For example, the insulator 412 preferably includes gallium oxide, hafnium oxide, oxide including aluminum and hafnium, oxynitride including aluminum and hafnium, oxide including silicon and hafnium, oxynitride including silicon and hafnium, or the like. The insulator 412 preferably has a stacked structure including silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with an insulator with a high relative dielectric constant, the stacked structure can have thermal stability and a high relative dielectric constant. For example, when aluminum oxide, gallium oxide, or hafnium oxide of the insulator 412 is provided on the insulator 406 c side, entry of silicon included in the silicon oxide or the silicon oxynitride into the semiconductor 406 b can be suppressed. When silicon oxide or silicon oxynitride is provided on the insulator 406 c side, for example, trap centers might be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. The trap centers can shift the threshold voltage of the transistor in the positive direction by trapping electrons in some cases.

The conductors 416 a 1 and 416 a 2 may each include a single layer or stacked layers of a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used: a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used. The conductor 417 a 1, the conductor 417 a 2, the conductor 418 a 1, the conductor 418 a 2, and the conductor 418 a 3 may be formed in a similar manner.

The conductors 404 and 413 may each include a single layer or stacked layers of a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used: a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

As the semiconductor 406 b, an oxide semiconductor is preferably used. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like can be used in some cases.

The insulator 406 a and the insulator 406 c are preferably oxides including one or more, or two or more elements other than oxygen included in the semiconductor 406 b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like can be used in some cases.

The semiconductor 406 b is an oxide semiconductor containing indium, for example. The oxide semiconductor 406 b can have high carrier mobility (electron mobility) by containing indium, for example. The semiconductor 406 b preferably contains an element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, magnesium, tungsten, and the like. Note that two or more of the above elements may be used in combination as the element M, in some cases. The element M is an element having high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium. The element M is an element that can increase the energy gap of the oxide semiconductor, for example. Furthermore, the semiconductor 406 b preferably contains zinc. When the oxide semiconductor contains zinc, the oxide semiconductor is easily crystallized, in some cases.

Note that the semiconductor 406 b is not limited to the oxide semiconductor containing indium. The semiconductor 406 b may be, for example, an oxide semiconductor which does not contain indium and contains zinc, an oxide semiconductor which does not contain indium and contains gallium, or an oxide semiconductor which does not contain indium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 406 b, an oxide with a wide energy gap may be used, for example. For example, the energy gap of the semiconductor 406 b is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, and further preferably greater than or equal to 3 eV and less than or equal to 3.5 eV.

As the semiconductor 406 b, an oxide having an electron affinity higher than those of the insulators 406 a and 406 c is used. For example, as the semiconductor 406 b, an oxide having an electron affinity higher than those of the insulators 406 a and 406 c by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, further preferably 0.15 eV or higher and 0.4 eV or lower is used. Note that the electron affinity refers to an energy gap between the vacuum level and the conduction band minimum.

When gate voltage is applied to such a transistor in which the insulator 406 a is placed under the semiconductor 406 b and the insulator 406 c is placed over the semiconductor 406 b, a channel is formed in the semiconductor 406 b whose electron affinity is the highest among the insulator 406 a, the semiconductor 406 b, and the insulator 406 c. Thus, a buried channel structure can be formed.

Here, in some cases, there is a mixed region of the insulator 406 a and the semiconductor 406 b between the insulator 406 a and the semiconductor 406 b. Furthermore, in some cases, there is a mixed region of the semiconductor 406 b and the insulator 406 c between the semiconductor 406 b and the insulator 406 c. The mixed region has a low density of defect states. For that reason, the stack of the insulator 406 a, the semiconductor 406 b, and the insulator 406 c has a band structure where energy at each interface and in the vicinity of the interface is changed continuously (continuous junction) (see FIG. 4). Note that boundaries of the insulator 406 a, the semiconductor 406 b, and the insulator 406 c are not clear in some cases.

At this time, electrons move mainly in the semiconductor 406 b, not in the insulator 406 a and the insulator 406 c.

As factors of inhibiting electron movement are decreased, the on-state current of the transistor can be increased. Electron movement is inhibited, for example, in the case where physical unevenness in a channel formation region is large.

To increase the on-state current of the transistor, for example, root mean square (RMS) roughness with a measurement area of 1 μm×1 μm of the top surface or the bottom surface of the semiconductor 406 b (a formation surface; here, the top surface of the insulator 406 a) is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) with the measurement area of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The maximum difference (P−V) with the measurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9 nm, further preferably less than 8 nm, still further preferably less than 7 nm. RMS roughness, Ra, and P−V can be measured using a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc.

The above three-layer structure is an example. For example, a stacked structure in which any one or more of the insulators described as examples of the insulator 406 a and the insulator 406 c is provided over or below the insulator 406 a or over or below the insulator 406 c may be employed.

<Structure of Oxide Semiconductor>

Structures of an oxide semiconductor that can be used as the above semiconductor will be described below.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.

<CAAC-OS>

First, a CAAC-OS will be described.

The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. The pellets are each larger than or equal to 1 nm, preferably larger than or equal to 3 nm, and further preferably larger than or equal to 6 nm.

A CAAC-OS observed with TEM will be described below. FIG. 5A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 5B is an enlarged Cs-corrected high-resolution TEM image of a region (1) in FIG. 5A. FIG. 5B shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS.

As shown in FIG. 5B, the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line in FIG. 5C. FIGS. 5B and 5C prove that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120 is illustrated by such a structure in which bricks or blocks are stacked (see FIG. 5D). The part in which the pellets are tilted as observed in FIG. 5C corresponds to a region 5161 shown in FIG. 5D.

FIG. 6A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 6B, 6C, and 6D are enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. 6A, respectively. FIGS. 6B, 6C, and 6D indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when the structure of a CAAC-OS including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 7A. This peak is attributed to the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray beam is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak is attributed to the (110) plane of the InGaZnO₄ crystal. In the case of the CAAC-OS, when analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (φ axis), as shown in FIG. 7B, a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO₄, when φ scan is performed with 2θ fixed at around 56°, as shown in FIG. 7C, six peaks which are attributed to crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO₄ crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown in FIG. 8A can be obtained. In this diffraction pattern, spots attributed to the (009) plane of an InGaZnO₄ crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 8B shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 8B, a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in FIG. 8B is considered to be attributed to the (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal. The second ring in FIG. 8B is considered to be attributed to the (110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. Impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources, for example. Furthermore, an oxygen vacancy in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, an oxide semiconductor with a carrier density of lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and is higher than or equal to 1×10⁻⁹/cm³ can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.

<nc-OS>

Next, an nc-OS will be described.

An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, bright regions in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases.

Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<a-like OS>

An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed.

The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.

An a-like OS (sample A), an nc-OS (sample B), and a CAAC-OS (sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of an InGaZnO₄ crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄. Each of lattice fringes corresponds to the a-b plane of the InGaZnO₄ crystal.

FIG. 9 shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 9 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) in FIG. 9, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3) in FIG. 9, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. It is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with a rhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³ and lower than 5.9 g/cm³. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked-layer film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

<Method 1 for Manufacturing Transistor>

A method for manufacturing the transistor of one embodiment of the present invention illustrated in FIGS. 1A to 1C will be described below with reference to FIGS. 10A to 10C, FIGS. 11A to 11C, FIGS. 12A to 12C, FIGS. 13A to 13C, FIGS. 14A to 14C, FIGS. 15A to 15C, FIGS. 16A to 16C, FIGS. 17A to 17C, and FIGS. 18A to 18C.

First, the substrate 400 is prepared.

Next, a conductor is deposited over the substrate 400 and is then processed by a photolithography method or the like to form the conductor 413. The conductor to be the conductor 413 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductor 413 may have a multilayer structure including a conductor that does not easily transmit oxygen. Then, an insulator to be the insulator 401 is deposited and polished by chemical mechanical polishing (CMP) or the like until part of the conductor 413 is exposed, to form the insulator 401 (see FIGS. 10A to 10C). The insulator 401 is preferably deposited using a tetraethoxysilane (TEOS; chemical formula: Si(OC₂H₅)₄) gas.

The conductor 413 may be formed by a different method as follows: an insulator to be the insulator 402 is deposited over the substrate 400, an opening is formed in the insulator 402, a conductive film to be the conductor 413 is formed over the insulator 402, and then CMP or the like is performed so that the conductor 413 is embedded in the opening of the insulator 402.

In the lithography method, first, a resist is exposed to light through a photomask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching through the resist mask is conducted. As a result, a conductor, semiconductor, insulator, or the like can be processed into a desired shape. The resist mask is formed by, for example, exposure of the resist to light using KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, or the like. Alternatively, a liquid immersion technique may be employed in which a portion between a substrate and a projection lens is filled with liquid (e.g., water) to perform light exposure. An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a mask is not necessary in the case of using an electron beam or an ion beam. Note that dry etching treatment such as ashing or wet etching treatment can be used for removal of the resist mask. Alternatively, wet etching treatment is performed in addition to dry etching treatment. Further alternatively, dry etching treatment is performed in addition to wet etching treatment.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel-plate-type electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel-plate-type electrodes may have a structure in which high-frequency power is applied to one of the parallel-plate-type electrodes. Alternatively, the capacitively coupled plasma etching apparatus may have a structure in which different high-frequency powers are applied to one of the parallel-plate-type electrodes. Alternatively, the capacitively coupled plasma etching apparatus may have a structure in which high-frequency powers with the same frequency are applied to the parallel-plate-type electrodes. Alternatively, the capacitively coupled plasma etching apparatus may have a structure in which high-frequency powers with different frequencies are applied to the parallel-plate-type electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used, for example.

Next, high-density plasma treatment may be performed as indicated by arrows in FIGS. 10B and 10C. The high-density plasma treatment is preferably performed in an oxygen atmosphere or a nitrogen atmosphere. The oxygen atmosphere is a gas atmosphere containing an oxygen atom and refers to atmospheres of oxygen, ozone, and nitrogen oxide (e.g., nitrogen monoxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, dinitrogen tetroxide, or dinitrogen pentoxide). In an oxygen atmosphere, an inert gas such as nitrogen or a rare gas (e.g., helium or argon) may be contained. With this high-density plasma treatment performed in an oxygen atmosphere, a Group 14 element such as carbon can be eliminated, for example. Furthermore, with the high-density plasma treatment in an oxygen atmosphere, an organic compound such as hydrocarbon is also easily eliminated from a treated object.

The high-density plasma treatment in a nitrogen atmosphere may be high-density plasma treatment in an atmosphere containing nitrogen and a rare gas, an atmosphere containing nitrogen, hydrogen, and a rare gas, or an atmosphere containing ammonia and a rare gas, for example. With this high-density plasma treatment in a nitrogen atmosphere, a surface of the treated object and its vicinity can be nitrided. The nitrided region can be formed to be extremely thin on the surface side of the treated object. This nitrided region can prevent diffusion of impurities.

After the high-density plasma treatment in an oxygen atmosphere is performed, the high-density plasma treatment in a nitrogen atmosphere may be performed. Alternatively, after the high-density plasma treatment in a nitrogen atmosphere is performed, the high-density plasma treatment in an oxygen atmosphere may be performed. Annealing treatment may be performed before or after each high-density plasma treatment. Note that it is in some cases preferable to let an enough amount of gas flow in order to increase the plasma density. When the gas amount is not enough, the deactivation rate of radicals becomes higher than the generation rate of radicals in some cases. For example, it is preferable in some cases to let a gas flow at 100 sccm or more, 300 sccm or more, or 800 sccm or more.

The high-density plasma treatment is performed using a microwave generated with a high-frequency generator that generates a wave having a frequency of, for example, more than or equal to 0.3 GHz and less than or equal to 3.0 GHz, more than or equal to 0.7 GHz and less than or equal to 1.1 GHz, or more than or equal to 2.2 GHz and less than or equal to 2.8 GHz (typically, 2.45 GHz). The treatment pressure can be higher than or equal to 10 Pa and lower than or equal to 5000 Pa, preferably higher than or equal to 200 Pa and lower than or equal to 1500 Pa, further preferably higher than or equal to 300 Pa and lower than or equal to 1000 Pa. The substrate temperature can be higher than or equal to 100° C. and lower than or equal to 600° C. (typically 400° C.). Furthermore, a mixed gas of oxygen and argon can be used.

For example, the high density plasma is generated using a 2.45 GHz microwave and preferably has an electron density of higher than or equal to 1×10¹¹/cm³ and lower than or equal to 1×10¹³/cm³, an electron temperature of 2 eV or lower, or an ion energy of 5 eV or lower. Such high-density plasma treatment produces radicals with low kinetic energy and causes little plasma damage, compared with conventional plasma treatment. Thus, formation of a film with few defects is possible. The distance between an antenna that generates the microwave and the treated object is longer than or equal to 5 mm and shorter than or equal to 120 mm, preferably longer than or equal to 20 mm and shorter than or equal to 60 mm.

Alternatively, a plasma power source that applies a radio frequency (RF) bias to a substrate may be provided. The frequency of the RF bias may be 13.56 MHz, 27.12 MHz, or the like, for example. The use of high-density plasma enables high-density oxygen ions to be produced, and application of the RF bias to the substrate allows oxygen ions generated by the high-density plasma to be efficiently introduced into the treated object. Therefore, it is preferable to perform the high-density plasma treatment while a bias is applied to the substrate.

Following the high-density plasma treatment, annealing treatment may be successively performed without an exposure to the air. Following annealing treatment, the high-density plasma treatment may be successively performed without an exposure to the air. By performing high-density plasma treatment and annealing treatment in succession, entry of impurities during the treatment can be suppressed. Moreover, by performing annealing treatment after the high-density plasma treatment in an oxygen atmosphere, unnecessary oxygen that is added into the treated object but is not used to fill oxygen vacancies can be eliminated. The annealing treatment may be performed by lamp annealing or the like, for example.

The treatment time of the high-density plasma treatment is preferably longer than or equal to 30 seconds and shorter than or equal to 120 minutes, longer than or equal to 1 minute and shorter than or equal to 90 minutes, longer than or equal to 2 minutes and shorter than or equal to 30 minutes, or longer than or equal to 3 minutes and shorter than or equal to 15 minutes.

The treatment time of the annealing treatment at a temperature of higher than or equal to 250° C. and lower than or equal to 800° C., higher than or equal to 300° C. and lower than or equal to 700° C., or higher than or equal to 400° C. and lower than or equal to 600° C. is preferably longer than or equal to 30 seconds and shorter than or equal to 120 minutes, longer than or equal to 1 minute and shorter than or equal to 90 minutes, longer than or equal to 2 minutes and shorter than or equal to 30 minutes, or longer than or equal to 3 minutes and shorter than or equal to 15 minutes.

Next, the insulator 402 is deposited (see FIGS. 11A to 11C). The insulator 402 may be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

Note that CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD method can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas.

In the case of a PECVD method, a high quality film can be obtained at relatively low temperature. Furthermore, a TCVD method does not use plasma and thus causes little plasma damage to an object. For example, a wiring, an electrode, an element (e.g., transistor or capacitor), or the like included in a semiconductor device might be charged up by receiving electric charges from plasma. In that case, accumulated electric charges might break the wiring, electrode, element, or the like included in the semiconductor device. Such damage caused by the exposure to plasma does not occur when using a TCVD method, and thus the yield of a semiconductor device can be increased. In addition, in a TCVD method, the exposure to plasma during the deposition is not performed and accordingly a film with few defects tends to be obtained.

An ALD method also causes little plasma damage to an object. An ALD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

Unlike in a deposition method in which particles ejected from a target or the like are deposited, a CVD method and an ALD method form a film by reaction at a surface of an object. Thus, a CVD method and an ALD method enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and can be favorably used for covering a surface of an opening with a high aspect ratio, for example. On the other hand, an ALD method has a low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method.

When a CVD method or an ALD method is used, the composition of a formed film can be controlled with a flow rate ratio of source gases. For example, by the CVD method or the ALD method, a film with a desired composition can be formed by adjusting the flow rate ratio of source gases. Moreover, with a CVD method or an ALD method, by changing the flow rate ratio of source gases while depositing the film, a film whose composition is continuously changed can be formed. In the case where the film is deposited while changing the flow rate ratio of source gases, as compared with the case where the film is deposited using a plurality of deposition chambers, the time taken for the film deposition can be reduced because the time taken for transfer and pressure adjustment is omitted. Thus, the productivity of semiconductor devices can be increased, in some cases.

The insulator 402 is preferably deposited using a TEOS gas.

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 11B and 11C.

Then, an insulator 406 d is deposited over the insulator 402 (see FIGS. 12A to 12C). The insulator 406 d can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is particularly preferable to use a facing-target sputtering apparatus. Note that in this specification and the like, deposition using a facing-target sputtering apparatus can also be referred to as vapor deposition sputtering (VDSP).

The use of the facing-target sputtering apparatus can reduce plasma damage during deposition of the insulator 406 d. Thus, oxygen vacancies in the film can be reduced. In addition, when using the facing-target sputtering apparatus, deposition in high vacuum is possible, which enables the impurity concentration (e.g., concentration of hydrogen, a rare gas (such as argon), or water) in the deposited insulator to be reduced.

Alternatively, a sputtering apparatus including an inductively coupled antenna conducting plate may be used. In that case, a film with a large area and high uniformity can be deposited with a high deposition rate.

The deposition is preferably performed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. As the gas containing nitrogen, nitrogen (N₂), dinitrogen monoxide (N₂O), ammonia (NH₃), or the like may be used, for example.

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 12B and 12C.

Next, a semiconductor to be the semiconductor 406 b is deposited over the insulator 406 d. The semiconductor to be the semiconductor 406 b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is particularly preferable to use a facing-target sputtering apparatus.

The use of the facing-target sputtering apparatus can reduce plasma damage during deposition of the semiconductor. Thus, oxygen vacancies in the film can be reduced. In addition, when using the facing-target sputtering apparatus, deposition in high vacuum is possible, which enables the impurity concentration (e.g., concentration of hydrogen, a rare gas (such as argon), or water) in the deposited semiconductor to be reduced.

Alternatively, a sputtering apparatus including an inductively coupled antenna conducting plate may be used. In that case, a film with a large area and high uniformity can be deposited with a high deposition rate.

The deposition is preferably performed using a gas containing oxygen, a rare gas, a gas containing nitrogen, or the like. As the gas containing nitrogen, nitrogen (N₂), dinitrogen monoxide (N₂O), ammonia (NH₃), or the like may be used, for example.

Next, first heat treatment is preferably performed. The first heat treatment can be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C. The first heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under a reduced pressure. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate eliminated oxygen. By the first heat treatment, crystallinity of the semiconductor can be increased and impurities such as hydrogen and water can be removed. Before or after the first heat treatment, the above-described high-density plasma treatment may be performed.

Next, the insulator 406 d and the semiconductor to be the semiconductor 406 b are processed by a photolithography method or the like to form a multilayer film including the insulator 406 a and the semiconductor 406 b (see FIGS. 13A to 13C). When the multilayer film is formed, the insulator 402 might also be etched and a thinned region might partly be formed. That is, the insulator 402 might have a shape including a projection in a region in contact with the multilayer film.

During the etching treatment of the above processing, impurities might enter the treated object. Removing such impurities that have entered during etching is critical, and thus second heat treatment is preferably performed. The second heat treatment can be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C. The second heat treatment is performed in a nitrogen atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The second heat treatment may be performed under a reduced pressure. Alternatively, the second heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate eliminated oxygen. By the second heat treatment, crystallinity of the semiconductor can be increased and impurities such as hydrogen and water can be removed from the semiconductor and the insulating film. Before or after the second heat treatment, the above-described high-density plasma treatment may be performed. Alternatively, without the second heat treatment, only the above-described high-density plasma treatment may be performed. After the second heat treatment, treatment for adding oxygen may be performed. As a method for adding oxygen, ion implantation, ion doping, or the like may be performed, for example.

For example, the above-described high-density plasma treatment may be performed in such a manner that high-density plasma treatment in a nitrogen atmosphere is performed and then high-density plasma treatment in an oxygen atmosphere is performed. In that case, it is preferable that there is no exposure to the air between the high-density plasma treatment in a nitrogen atmosphere and the high-density plasma treatment in an oxygen atmosphere so that entry of impurities or the like can be suppressed.

By performing the heat treatment, the high-density plasma treatment, or the like after the multilayer film including the insulator 406 a and the semiconductor 406 b is formed, impurities such as hydrogen that have entered the insulator 402, the insulator 406 a, the semiconductor 406 b, and the like during the etching can be removed.

Next, a conductor is deposited. The conductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a resist is formed over the conductor by a photolithography method or the like, and etching is performed by a dry etching method or the like using the resist as a mask to form a conductor 415.

The conductor 415 has a shape covering the multilayer film. Due to the partial damage of a side surface of the insulator 406 a and top and side surfaces of the semiconductor 406 b during the deposition of the conductor over the multilayer film, a low-resistance region might be formed. The low-resistance region that is formed in part of the insulator 406 a and the semiconductor 406 b can decrease contact resistance between the conductor 415 and the semiconductor 406 b.

Next, the insulator 410 is deposited (see FIGS. 14A to 14C). The insulator 410 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the insulator 410 can be formed by a spin coating method, a dipping method, a droplet discharging method (such as an ink-jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like. The insulator 410 is preferably deposited using a TEOS gas.

The insulator 410 may be formed to have a flat top surface. For example, the insulator 410 may have a flat top surface immediately after the film deposition. Alternatively, for example, the top surface of the insulator 410 may have flatness by being formed through removal of the upper portion of an insulator and the like after the film deposition so that the top surface becomes parallel to a reference surface such as a rear surface of the substrate. This treatment is referred to as planarization treatment. As the planarization treatment, there are chemical mechanical polishing treatment, dry etching treatment, and the like. However, the top surface of the insulator 410 is not necessarily flat.

Next, a resist mask is formed over the insulator 410 by a lithography method or the like. Here, an organic coating film may be provided between the insulator 410 and the resist mask in order to improve the adhesion between the top surface of the insulator 410 and the resist mask.

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 14B and 14C.

Then, the insulator 410 is subjected to first processing by a dry etching method or the like until an opening reaches a top surface of the conductor 415. As the dry etching method, any of the above-described dry etching apparatuses can be used; however, a dry etching apparatus in which high-frequency power sources with different frequencies are connected to the parallel-plate-type electrodes is preferably used.

Next, the conductor 415 is subjected to second processing by a dry etching method or the like so as to be divided into the conductor 416 a 1 and the conductor 416 a 2. Note that the insulator 410 and the conductor 415 may be processed in the same photolithography process. Processing in the same photolithography process can reduce the number of steps. Thus, a semiconductor device including the transistor can be manufactured with high productivity. Alternatively, the insulator 410 and the conductor 415 may be processed in different photolithography processes. Processing in different photolithography processes may facilitate formation of films with different shapes (see FIGS. 15A to 15C).

At this time, the semiconductor 406 b has a region that is exposed. Part of the exposed region of the semiconductor 406 b is removed by the second processing in some cases. Furthermore, impurity elements such as residual components of the etching gas are attached to the exposed semiconductor 406 b in some cases. For example, when a chlorine-based gas is used as the etching gas, chlorine or the like might be attached. When a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, or the like might be attached. The impurity elements attached to the exposed surface of the semiconductor 406 b are preferably reduced. The impurity can be reduced by, for example, cleaning treatment using a dilute hydrofluoric acid or the like, cleaning treatment using ozone or the like, or cleaning treatment using ultraviolet light or the like. Note that a plurality of types of cleaning treatments may be used in combination. Accordingly, the exposed surface of the semiconductor 406 b, that is, the channel formation region has high resistance.

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 15B and 15C. With the high-density plasma treatment, a reaction product (also referred to as “rabbit ear”), which is formed on a side surface of the insulator 410 or the like at the time of processing the insulator 410 and the conductor 415, can be removed.

In the case of finishing the fabrication up to FIGS. 15A to 15C, a bottom-gate transistor in which the conductor 413, the insulator 402, the conductor 416 a 1, and the conductor 416 a 2 serve as a gate electrode, a gate insulator, a source electrode, and a drain electrode, respectively, for example, is formed.

Next, the insulator 406 c is deposited. The insulator 406 c can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 406 c may be deposited in a manner similar to that of the insulator 406 a. After the insulator 406 c is deposited, the above-described high-density plasma treatment may be performed.

Next, the insulator 412 is deposited over the insulator 406 c (see FIGS. 16A to 16C). The insulator 412 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 412 is preferably deposited using a TEOS gas.

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 16B and 16C.

Next, a conductor to be the conductor 404 is deposited. The conductor to be the conductor 404 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductor to be the conductor 404 is deposited so as to fill an opening provided in the insulator 410. Therefore, a CVD method (in particular, an MCVD method) is preferably used. A stacked-layer film of a conductor deposited by an ALD method or the like and a conductor deposited by a CVD method is preferred in some cases to increase adhesion of the conductor deposited by the CVD method. For example, a stacked-layer film where titanium nitride and tungsten are formed in this order or the like may be used.

Then, polishing is performed by CMP or the like until a surface of the insulator 410 is exposed, so that the conductor 404 is formed (see FIGS. 17A to 17C).

Accordingly, the conductor 404 serving as the gate electrode can be formed in a self-aligned manner without using a lithography method. The conductor 404 serving as the gate electrode can be formed without considering the alignment accuracy of the conductor 404 serving as the gate electrode and the conductors 416 a 1 and 416 a 2 serving as the source and drain electrodes; as a result, the area of the semiconductor device can be reduced. Furthermore, because the lithography process is not necessary, an improvement in productivity due to simplification of the process is expected.

Polishing is not necessarily performed until the surface of the insulator 410 is exposed. The conductor 404 may be formed by performing polishing until a surface of the insulator 412 is exposed. The conductor 404 may be formed by performing polishing until a surface of the insulator 406 c is exposed. The insulator 410, the insulator 412, or the insulator 406 c preferably includes an insulator functioning as a CMP stopper.

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 17B and 17C.

Next, an opening which reaches the conductor 416 a 1 and an opening which reaches the conductor 416 a 2 are formed in the insulator 410 (see FIGS. 18A to 18C).

Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 18B and 18C. With the high-density plasma treatment, a reaction product (also referred to as “rabbit ear”) which is formed on the side surface of the insulator 410 or the like at the time of processing the insulator 410 can be removed.

Then, the conductor 417 a 1 and the conductor 417 a 2 which fill the openings and the conductor 418 a 1, the conductor 418 a 2, and the conductor 418 a 3 which are connected to the conductor 417 a 1, the conductor 417 a 2, and the conductor 417 a 3, respectively, are formed.

In the above-described manner, the transistor illustrated in FIGS. 1A to 1C can be manufactured.

In this embodiment, one embodiment of the present invention has been described. However, one embodiment of the present invention is not limited to the above-described embodiment. That is, since various embodiments of the present invention are disclosed in this embodiment and the other embodiments, one embodiment of the present invention is not limited to a specific embodiment. An example in which an oxide semiconductor is used as a semiconductor has been described as one embodiment of the present invention; however, one embodiment of the present invention is not limited to this example. Depending on cases or conditions, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used in one embodiment of the present invention.

The structure and method described in this embodiment can be used in appropriate combination with any of the other structures and methods described in the other embodiments.

Embodiment 2 Transistor Structure 2

A transistor having a structure different from that illustrated in FIGS. 1A to 1C and a manufacturing method of the transistor will be described below with reference to FIGS. 19A to 19C, FIGS. 20A to 20C, FIGS. 21A to 21C, FIGS. 22A to 22C, and FIGS. 23A to 23C. FIGS. 19A to 19C are a top view and cross-sectional views of a semiconductor device of one embodiment of the present invention. FIG. 19A is the top view. FIG. 19B is the cross-sectional view taken along a dashed-dotted line A1-A2 in FIG. 19A. FIG. 19C is the cross-sectional view taken along a dashed-dotted line A3-A4 in FIG. 19A. Note that in the top view of FIG. 19A, some components are not illustrated for simplification of the drawing.

The transistor of this embodiment is different from that illustrated in FIGS. 1A to 1C in the shape of the conductors serving as the source and drain electrodes. The transistor illustrated in FIGS. 19A to 19C has a structure in which a conductor 416 b 1 and a conductor 416 b 2 serving as a source and drain electrodes are formed only over the top surface of the semiconductor 406 b. For the other components, the description of the transistor illustrated in FIGS. 1A to 1C is referred to.

<Method 2 for Manufacturing Transistor>

A method for manufacturing the transistor illustrated in FIGS. 19A to 19C will be described below with reference to FIGS. 20A to 20C, FIGS. 21A to 21C, FIGS. 22A to 22C, and FIGS. 23A to 23C.

First, the substrate 400 is prepared. Next, a conductor is deposited over the substrate 400 and is then processed by a photolithography method or the like to form the conductor 413. Then, the insulator 402 is deposited.

Next, an insulator to be the insulator 406 a is deposited over the insulator 402. Then, the semiconductor to be the semiconductor 406 b is deposited over the insulator to be the insulator 406 a.

Next, first heat treatment is preferably performed. The first heat treatment may be performed in a manner similar to that of Embodiment 1. Before or after the first heat treatment, high-density plasma treatment may be performed in a manner similar to that of Embodiment 1.

Next, a conductor to be a conductor 414 is deposited over the semiconductor to be the semiconductor 406 b. The conductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Then, the insulator to be the insulator 406 a, the semiconductor to be the semiconductor 406 b, and the conductor to be the conductor 414 are processed by a lithography method or the like to form a multilayer film including the insulator 406 a, the semiconductor 406 b, and the conductor 414 (see FIGS. 20A to 20C). Due to the damage of the top surface of the semiconductor to be the semiconductor 406 b during the deposition of the conductor, a low-resistance region might be formed. The low-resistance region that is formed in part of the semiconductor 406 b can decrease contact resistance between the conductor 414 and the semiconductor 406 b. When the multilayer film is formed, the insulator 402 might also be etched, and a thinned region might partly be formed. That is, the insulator 402 might have a shape including a projection in a region in contact with the multilayer film. Next, the above-describe high-density plasma treatment may be performed.

Then, the insulator 410 is deposited over the conductor 414 (see FIGS. 21A to 21C). Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 21B and 21C.

Then, the insulator 410 and the conductor 414 are processed so that the conductor 414 is divided into the conductor 416 b 1 and the conductor 416 b 2 (see FIGS. 22A to 22C). Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 22B and 22C.

In the case of finishing the fabrication up to FIGS. 22A to 22C, a bottom-gate transistor in which the conductor 413, the insulator 402, the conductor 416 b 1, and the conductor 416 b 2 serve as a gate electrode, a gate insulator, a source electrode, and a drain electrode, respectively, for example, is formed.

Then, the insulator 406 c, the insulator 412, and the conductor 404 are formed in a manner similar to that of Embodiment 1 (see FIGS. 23A to 23C). Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 23B and 23C.

Subsequent steps may be performed in a manner similar to that of the method for manufacturing the transistor described in Embodiment 1.

In the above-described manner, the transistor illustrated in FIGS. 19A to 19C can be manufactured.

The structure and method described in this embodiment can be used in appropriate combination with any of the other structures and methods described in the other embodiments.

Embodiment 3 Transistor Structure 3

A transistor having a structure different from that illustrated in FIGS. 1A to 1C and a manufacturing method of the transistor will be described below with reference to FIGS. 24A to 24C, FIGS. 25A to 25C, FIGS. 26 to 26C, FIGS. 27A to 27C, and FIGS. 28A to 28C. FIGS. 24A to 24C are a top view and cross-sectional views of a semiconductor device of one embodiment of the present invention. FIG. 24A is the top view. FIG. 24B is the cross-sectional view taken along a dashed-dotted line A1-A2 in FIG. 24A. FIG. 24C is the cross-sectional view taken along a dashed-dotted line A3-A4 in FIG. 24A. Note that in the top view of FIG. 24A, some components are not illustrated for simplification of the drawing.

The transistor of this embodiment is different from that illustrated in FIGS. 1A to 1C in the shape of the conductor 404. In the transistor illustrated in FIGS. 24A to 24C, unlike in the transistor illustrated in FIGS. 1A to 1C, the conductor 404 serving as a gate electrode is formed by a lithography method. For the other components, the description of the transistor illustrated in FIGS. 1A to 1C is referred to.

<Method 3 for Manufacturing Transistor>

A method for manufacturing the transistor illustrated in FIGS. 24A to 24C will be described below with reference to FIGS. 25A to 25C, FIGS. 26A to 26C, FIGS. 27A to 27C, and FIGS. 28A to 28C.

First, the steps up to and including the step illustrated in FIGS. 13A to 13C in Embodiment 1 are performed similarly.

Then, a conductor 411 is deposited (see FIGS. 25A to 25C). The conductor 411 may be deposited in a manner similar to that of the conductor 416 a 1, the conductor 416 a 2, and the like.

Then, the conductor 411 is processed by a photolithography method or the like to form the conductor 416 a 1 and the conductor 416 a 2 (see FIGS. 26A to 26C). Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 26B and 26C.

In the case of finishing the fabrication up to FIGS. 26A to 26C, a bottom-gate transistor in which the conductor 413, the insulator 402, the conductor 416 a 1, and the conductor 416 a 2 serve as a gate electrode, a gate insulator, a source electrode, and a drain electrode, respectively, for example, is formed.

Then, an insulator 406 f and an insulator 419 are deposited (see FIGS. 27A to 27C). Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 27B and 27C.

Next, a conductor to be the conductor 404 is formed and is then processed by a photolithography method or the like to form the conductor 404. Furthermore, by using a resist used in the photolithography method or the like or the conductor 404, the insulator 419 is processed into the insulator 412. Moreover, by using the resist, the conductor 404, or the insulator 412, the insulator 406 f is processed into the insulator 406 c. The insulator 406 c, the insulator 412, and the conductor 404 have the same shape when seen from the above, but a transistor of one embodiment of the present invention is not limited to this shape. For example, the insulator 406 c, the insulator 412, and the conductor 404 may be processed using different resists. For example, after the insulator 412 is formed, the conductor to be the conductor 404 may be formed; or after the conductor 404 is formed, a resist or the like may be formed over the insulator to be the insulator 412. For example, the insulator 406 c may be shared between adjacent transistors or the like. The insulator 412 and the insulator 406 c may protrude from an edge of the conductor 404. The processing of the insulator 419 and the insulator 406 f may be omitted.

Then, the insulator 410 is deposited (see FIGS. 28A to 28C). Next, the above-described high-density plasma treatment may be performed as indicated by arrows in FIGS. 28B and 28C.

Subsequent steps may be performed in a manner similar to that of the method for manufacturing the transistor described in Embodiment 1.

In the above-described manner, the transistor illustrated in FIGS. 24A to 24C can be manufactured.

The structure and method described in this embodiment can be used in appropriate combination with any of the other structures and methods described in the other embodiments.

Embodiment 4 Manufacturing Apparatus

A manufacturing apparatus which performs high-density plasma treatment according to one embodiment of the present invention will be described below.

First, a structure of a manufacturing apparatus which hardly allows entry of impurities in manufacturing a semiconductor device or the like is described with reference to FIG. 29, FIG. 30, and FIG. 31.

FIG. 29 is a top view schematically illustrating a single wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 including a cassette port 2761 for holding a substrate and an alignment port 2762 for performing alignment of a substrate, an atmosphere-side substrate transfer chamber 2702 through which a substrate is transferred from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703 a where a substrate is carried and the pressure inside the chamber is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703 b where a substrate is carried out and the pressure inside the chamber is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 through which a substrate is transferred in a vacuum, and chambers 2706 a, 2706 b, 2706 c, and 2706 d.

The atmosphere-side substrate transfer chamber 2702 is connected to the load lock chamber 2703 a and the unload lock chamber 2703 b, the load lock chamber 2703 a and the unload lock chamber 2703 b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chambers 2706 a, 2706 b, 2706 c, and 2706 d.

Note that gate valves GV are provided in connecting portions between the chambers so that each chamber excluding the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702 can be independently kept in a vacuum state. In addition, the atmosphere-side substrate transfer chamber 2702 is provided with a transfer robot 2763 a, and the transfer chamber 2704 is provided with a transfer robot 2763 b. With the transfer robot 2763 a and the transfer robot 2763 b, a substrate can be transferred inside the manufacturing apparatus 2700.

In the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, the back pressure (total pressure) is, for example, lower than or equal to 1×10⁻⁴ Pa, preferably lower than or equal to 3×10⁻⁵ Pa, further preferably lower than or equal to 1×10⁻⁵ Pa. In the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is, for example, lower than or equal to 3×10⁻⁵ Pa, preferably lower than or equal to 1×10⁻⁵ Pa, further preferably lower than or equal to 3×10⁻⁶ Pa. Moreover, in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is, for example, lower than or equal to 3×10⁻⁵ Pa, preferably lower than or equal to 1×10⁻⁵ Pa, further preferably lower than or equal to 3×10⁻⁶ Pa. Further, in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is, for example, lower than or equal to 3×10⁻⁵ Pa, preferably lower than or equal to 1×10⁻⁵ Pa, further preferably lower than or equal to 3×10⁻⁶ Pa.

Note that the total pressure and the partial pressure in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d can be measured using a mass analyzer. For example, Qulee CGM-051, a quadrupole mass analyzer (also referred to as Q-mass) manufactured by ULVAC, Inc. can be used.

Moreover, the transfer chamber 2704 and each of the chambers 2706 a to 2706 d preferably have a small amount of external leakage or internal leakage. For example, in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, the leakage rate is less than or equal to 3×10⁻⁶ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s. For example, the leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is less than or equal to 1×10⁻⁷ Pa·m³/s, preferably less than or equal to 3×10⁻⁸ Pa·m³/s. For example, the leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is less than or equal to 1×10⁻⁵ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s. For example, the leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is less than or equal to 3×10⁻⁶ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s.

Note that a leakage rate can be derived from the total pressure and partial pressure measured using the mass analyzer. The leakage rate depends on external leakage and internal leakage. The external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like. The internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or due to released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage in order that the leakage rate can be set to be less than or equal to the above-mentioned value.

For example, open/close portions of the transfer chamber 2704 and the chambers 2706 a to 2706 d can be sealed with a metal gasket. For the metal gasket, metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket realizes higher adhesion than an O-ring, and can reduce the external leakage. Furthermore, with the use of the metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, which is in the passive state, the release of gas containing impurities released from the metal gasket is suppressed, so that the internal leakage can be reduced.

For a member of the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a small amount of gas containing impurities, is used. Alternatively, an alloy containing iron, chromium, nickel, or the like covered with the above material may be used. The alloy containing iron, chromium, nickel, or the like is rigid, resistant to heat, and suitable for processing. Here, when surface unevenness of the member is decreased by polishing or the like to reduce the surface area, the release of gas can be reduced.

Alternatively, the above member of the manufacturing apparatus 2700 may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The member of the manufacturing apparatus 2700 is preferably formed using only metal when possible. For example, in the case where a viewing window formed of quartz or the like is provided, it is preferable that the surface of the viewing window be thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like so as to suppress release of gas.

When an adsorbed substance is present in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, although the adsorbed substance does not affect the pressure in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d because it is adsorbed onto an inner wall or the like, the adsorbed substance causes a release of gas when the inside of the transfer chamber 2704 and each of the chambers 2706 a to 2706 d is evacuated. Therefore, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d be desorbed as much as possible and exhaust be performed in advance with the use of a pump with high exhaust capability. Note that the transfer chamber 2704 and each of the chambers 2706 a to 2706 d may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold. The baking can be performed at a temperature of higher than or equal to 100° C. and lower than or equal to 450° C. At this time, when the adsorbed substance is removed while an inert gas is introduced into the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, the desorption rate of water or the like, which is difficult to desorb simply by exhaust, can be further increased. Note that when the inert gas that is introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, a rare gas is preferably used as the inert gas.

Alternatively, treatment for evacuating the inside of the transfer chamber 2704 and each of the chambers 2706 a to 2706 d is preferably performed a certain period of time after heated oxygen, a heated inert gas such as a heated rare gas, or the like is introduced to increase the pressure in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d. The introduction of the heated gas can desorb the adsorbed substance in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, and the impurities present in the transfer chamber 2704 and each of the chambers 2706 a to 2706 d can be reduced. Note that an advantageous effect can be achieved when this treatment is repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times. Specifically, an inert gas, oxygen, or the like with a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. is introduced to the transfer chamber 2704 and each of the chambers 2706 a to 2706 d, so that the pressure therein can be kept to be higher than or equal to 0.1 Pa and lower than or equal to 10 kPa, preferably higher than or equal to 1 Pa and lower than or equal to 1 kPa, further preferably higher than or equal to 5 Pa and lower than or equal to 100 Pa in the time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the inside of the transfer chamber 2704 and each of the chambers 2706 a to 2706 d is evacuated in the time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Next, the chambers 2706 b and 2706 c are described with reference to a schematic cross-sectional view of FIG. 30.

The chambers 2706 b and 2706 c are chambers capable of performing high-density plasma treatment on an object, for example. Because the chambers 2706 b and 2706 c have a common structure with the exception of the atmosphere used in the high-density plasma treatment, they are collectively described below.

The chambers 2706 b and 2706 c each include a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. A gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power source 2816, a vacuum pump 2817, and a valve 2818 are provided outside the chambers 2706 b and 2706 c.

The high-frequency generator 2803 is connected to the mode converter 2805 through the waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 through the waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. Further, the gas supply source 2801 is connected to the mode converter 2805 through the valve 2802. Gas is transferred to the chambers 2706 b and 2706 c through the gas pipe 2806 which runs through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas or the like from the chambers 2706 b and 2706 c through the valve 2818 and the exhaust port 2819. The high-frequency power source 2816 is connected to the substrate holder 2812 through the matching box 2815.

The substrate holder 2812 has a function of holding a substrate 2811. For example, the substrate holder 2812 has a function of an electrostatic chuck or a mechanical chuck for holding the substrate 2811. In addition, the substrate holder 2812 has a function of an electrode to which electric power is supplied from the high-frequency power source 2816. The substrate holder 2812 includes a heating mechanism 2813 therein and thus has a function of heating the substrate 2811.

As the vacuum pump 2817, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbomolecular pump, or the like can be used, for example. In addition to the vacuum pump 2817, a cryotrap may be used as well. The combinational use of the cryopump and the cryotrap allows water to be efficiently exhausted and is particularly preferable.

For example, the heating mechanism 2813 may be a heating mechanism which uses a resistance heater or the like for heating. Alternatively, a heating mechanism which utilizes heat conduction or heat radiation from a medium such as a heated gas for heating may be used. For example, rapid thermal annealing (RTA) such as gas rapid thermal annealing (GRTA) or lamp rapid thermal annealing (LRTA) can be used. In GRTA, heat treatment is performed using a high-temperature gas. An inert gas is used as the gas.

The gas supply source 2801 may be connected to a purifier through a mass flow controller. As the gas, a gas whose dew point is −80° C. or lower, preferably −100° C. or lower is preferably used. For example, an oxygen gas, a nitrogen gas, or a rare gas (e.g., an argon gas) may be used.

As the dielectric plate 2809, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), or the like may be used, for example. A protective layer may be further formed on a surface of the dielectric plate 2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like may be used. The dielectric plate 2809 is exposed to an especially high density region of high-density plasma 2810 that is to be described later. Therefore, the protective layer can reduce the damage and consequently prevent an increase of particles or the like during the treatment.

The high-frequency generator 2803 has a function of generating a microwave with a frequency of, for example, more than or equal to 0.3 GHz and less than or equal to 3.0 GHz, more than or equal to 0.7 GHz and less than or equal to 1.1 GHz, or more than or equal to 2.2 GHz and less than or equal to 2.8 GHz. The microwave generated by the high-frequency generator 2803 is propagated to the mode converter 2805 through the waveguide 2804. The mode converter 2805 converts the microwave propagated in the TE mode into a microwave in the TEM mode. Then, the microwave is propagated to the slot antenna plate 2808 through the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwave propagates through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and the high-density plasma 2810 can be generated. The high-density plasma 2810 includes ions and radicals depending on the gas species supplied from the gas supply source 2801. For example, oxygen radicals, nitrogen radicals, or the like are included.

At this time, the quality of a film or the like over the substrate 2811 can be modified by the ions and radicals generated in the high-density plasma 2810. Note that it is preferable in some cases to apply a bias to the substrate 2811 using the high-frequency power source 2816. As the high-frequency power source 2816, a radio frequency (RF) power source with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used, for example. The application of a bias to the substrate allows ions in the high-density plasma 2810 to efficiently reach a deep portion of an opening of the film or the like over the substrate 2811.

For example, in the chamber 2706 b, oxygen radical treatment using the high-density plasma 2810 can be performed by introducing oxygen from the gas supply source 2801. In the chamber 2706 c, nitrogen radical treatment using the high-density plasma 2810 can be performed by introducing nitrogen from the gas supply source 2801.

Next, the chambers 2706 a and 2706 d are described with reference to a schematic cross-sectional view of FIG. 31.

The chambers 2706 a and 2706 d are chambers capable of irradiating an object with an electromagnetic wave, for example. Because the chambers 2706 a and 2706 d have a common structure with the exception of the kind of the electromagnetic wave, they are collectively described below.

The chambers 2706 a and 2706 d each include one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. A gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chambers 2706 a and 2706 d.

The gas supply source 2821 is connected to the gas inlet 2823 through the valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 through the valve 2829. The lamp 2820 is provided to face the substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 includes a heating mechanism 2826 therein and thus has a function of heating the substrate 2824.

As the lamp 2820, a light source having a function of emitting an electromagnetic wave such as visible light or ultraviolet light may be used, for example. For example, a light source having a function of emitting an electromagnetic wave which has a peak in a wavelength region of longer than or equal to 10 nm and shorter than or equal to 2500 nm, longer than or equal to 500 nm and shorter than or equal to 2000 nm, or longer than or equal to 40 nm and shorter than or equal to 340 nm may be used.

As the lamp 2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp may be used, for example.

For example, part of or the whole electromagnetic wave emitted from the lamp 2820 is absorbed by the substrate 2824, so that the quality of a film or the like over the substrate 2824 can be modified. For example, defects can be generated or reduced or impurities can be removed. When the substrate 2824 absorbs the electromagnetic wave while being heated, generation or reduction of defects or removal of impurities can be efficiently performed.

Alternatively, for example, the electromagnetic wave emitted from the lamp 2820 may cause heat generation in the substrate holder 2825, by which the substrate 2824 may be heated. In this case, the heating mechanism 2826 inside the substrate holder 2825 may be omitted.

For the vacuum pump 2828, the description of the vacuum pump 2817 is referred to. For the heating mechanism 2826, the description of the heating mechanism 2813 is referred to. For the gas supply source 2821, the description of the gas supply source 2801 is referred to.

With the above-described manufacturing apparatus, the quality of a film can be modified while the entry of impurities into an object suppressed.

The structure and method described in this embodiment can be used in appropriate combination with any of the other structures and methods described in the other embodiments.

Embodiment 5 Memory Device 1

Examples of a semiconductor device (memory device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is shown in FIGS. 32A and 32B.

The semiconductor device illustrated in FIG. 32A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that any of the above-described transistors can be used as the transistor 3300.

Note that the transistor 3300 is preferably a transistor with a low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 3300. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period at a predetermined node of the semiconductor device. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low.

In FIG. 32A, a first wiring 3001 is electrically connected to a source of the transistor 3200. A second wiring 3002 is electrically connected to a drain of the transistor 3200. A third wiring 3003 is electrically connected to one of the source and the drain of the transistor 3300. A fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one electrode of the capacitor 3400. A fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400.

The semiconductor device in FIG. 32A has a feature that the potential of the gate of the transistor 3200 can be retained, and thus enables writing, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to a node FG where the gate of the transistor 3200 and the one electrode of the capacitor 3400 are electrically connected to each other. That is, a predetermined electric charge is supplied to the gate of the transistor 3200 (writing). Here, one of two kinds of electric charges providing different potential levels (hereinafter referred to as a low-level electric charge and a high-level electric charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is off, so that the transistor 3300 is turned off. Thus, the electric charge is held at the node FG (retaining).

Since the off-state current of the transistor 3300 is low, the electric charge of the node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring 3005 while a predetermined potential (a constant potential) is supplied to the first wiring 3001, whereby the potential of the second wiring 3002 varies depending on the amount of electric charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor 3200, an apparent threshold voltage V_(th) _(_) _(H) at the time when the high-level electric charge is given to the gate of the transistor 3200 is lower than an apparent threshold voltage V_(th) _(_) _(L) at the time when the low-level electric charge is given to the gate of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 which is needed to make the transistor 3200 be in “on state.” Thus, the potential of the fifth wiring 3005 is set to a potential V₀ which is between V_(th) _(_) _(H) and V_(th) _(_) _(L) whereby electric charge supplied to the node FG can be determined. For example, in the case where the high-level electric charge is supplied to the node FG in writing and the potential of the fifth wiring 3005 is V₀ (>V_(th) _(_) _(H)), the transistor 3200 is brought into “on state.” In the case where the low-level electric charge is supplied to the node FG in writing, even when the potential of the fifth wiring 3005 is V₀ (<V_(th) _(_) _(L)), the transistor 3200 still remains in “off state.” Thus, the data retained in the node FG can be read by determining the potential of the second wiring 3002.

Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. The fifth wiring 3005 of memory cells from which data is not read may be supplied with a potential at which the transistor 3200 is turned off regardless of the electric charge supplied to the node FG, that is, a potential lower than V_(th) _(_) _(H), whereby only data of a desired memory cell can be read. Alternatively, the fifth wiring 3005 of the memory cells from which data is not read may be supplied with a potential at which the transistor 3200 is brought into “on state” regardless of the electric charge supplied to the node FG, that is, a potential higher than V_(th) _(_) _(L), whereby only data of a desired memory cell can be read.

<Structure 1 of Semiconductor Device>

FIG. 33 is a cross-sectional view of the semiconductor device in FIG. 32A. The semiconductor device shown in FIG. 33 includes the transistor 3200, the transistor 3300, and the capacitor 3400. The transistor 3300 and the capacitor 3400 are provided over the transistor 3200. Although an example where the transistor illustrated in FIGS. 1A to 1C is used as the transistor 3300 is shown, a semiconductor device of one embodiment of the present invention is not limited to this example. The description of the above-described transistors can be referred to as appropriate.

The transistor 3200 illustrated in FIG. 33 is a transistor using a semiconductor substrate 450. The transistor 3200 includes a region 474 a in the semiconductor substrate 450, a region 474 b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

In the transistor 3200, the regions 474 a and 474 b have a function of a source region and a drain region. The insulator 462 has a function of a gate insulator. The conductor 454 has a function of a gate electrode. Therefore, the resistance of a channel formation region can be controlled by the potential applied to the conductor 454. In other words, conduction or non-conduction between the region 474 a and the region 474 b can be controlled by the potential applied to the conductor 454.

For the semiconductor substrate 450, a single-material semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like may be used, for example. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.

For the semiconductor substrate 450, a semiconductor substrate including impurities imparting n-type conductivity is used. However, a semiconductor substrate including impurities imparting p-type conductivity may be used as the semiconductor substrate 450. In that case, a well including impurities imparting the n-type conductivity may be provided in a region where the transistor 3200 is formed. Alternatively, the semiconductor substrate 450 may be an i-type semiconductor substrate.

The top surface of the semiconductor substrate 450 preferably has a (110) plane. Thus, on-state characteristics of the transistor 3200 can be improved.

The regions 474 a and 474 b are regions including impurities imparting the p-type conductivity. Accordingly, the transistor 3200 has a structure of a p-channel transistor.

Although the transistor 3200 being a p-channel transistor is described, the transistor 3200 may be an n-channel transistor.

The transistor 3200 is separated from an adjacent transistor by the region 460 and the like. The region 460 is an insulating region.

The semiconductor illustrated in FIG. 33 includes an insulator 464, an insulator 466, an insulator 468, an insulator 470, an insulator 472, an insulator 475, the insulator 402, the insulator 410, an insulator 465, an insulator 467, an insulator 469, an insulator 498, a conductor 480 a, a conductor 480 b, a conductor 480 c, a conductor 478 a, a conductor 478 b, a conductor 478 c, a conductor 476 a, a conductor 476 b, a conductor 476 c, a conductor 479 a, a conductor 479 b, a conductor 479 c, a conductor 477 a, a conductor 477 b, a conductor 477 c, a conductor 484 a, a conductor 484 b, a conductor 484 c, a conductor 484 d, a conductor 483 a, a conductor 483 b, a conductor 483 c, a conductor 483 d, a conductor 485 a, a conductor 485 b, a conductor 485 c, a conductor 485 d, a conductor 487 a, a conductor 487 b, a conductor 487 c, a conductor 488 a, a conductor 488 b, a conductor 488 c, a conductor 490 a, a conductor 490 b, a conductor 489 a, a conductor 489 b, a conductor 491 a, a conductor 491 b, a conductor 491 c, a conductor 492 a, a conductor 492 b, a conductor 492 c, a conductor 494, a conductor 496, an insulator 406 a, a semiconductor 406 b, and an insulator 406 c.

The insulator 464 is provided over the transistor 3200. The insulator 466 is over the insulator 464. The insulator 468 is over the insulator 466. The insulator 470 is placed over the insulator 468. The insulator 472 is placed over the insulator 470. The insulator 475 is placed over the insulator 472. The transistor 3300 is provided over the insulator 475. The capacitor 3400 is provided over the insulator 465. The insulator 469 is provided over the capacitor 3400.

The insulator 464 includes an opening reaching the region 474 a, an opening reaching the region 474 b, and an opening reaching the conductor 454, in which the conductor 480 a, the conductor 480 b, and the conductor 480 c are embedded, respectively.

In addition, the insulator 466 includes an opening reaching the conductor 480 a, an opening reaching the conductor 480 b, and an opening reaching the conductor 480 c, in which the conductor 478 a, the conductor 478 b, and the conductor 478 c are embedded, respectively.

In addition, the insulator 468 includes an opening reaching the conductor 478 a, an opening reaching the conductor 478 b, and an opening reaching the conductor 478 c, in which the conductor 476 a, the conductor 476 b, and the conductor 476 c are embedded, respectively.

The conductor 479 a in contact with the conductor 476 a, the conductor 479 b in contact with the conductor 476 b, and the conductor 479 c in contact with the conductor 476 c are over the insulator 468. The insulator 472 includes an opening reaching the conductor 479 a through the insulator 470, an opening reaching the conductor 479 b through the insulator 470, and an opening reaching the conductor 479 c through the insulator 470. In the openings, the conductor 477 a, the conductor 477 b, and the conductor 477 c are embedded.

The insulator 475 includes an opening overlapping with the channel formation region of the transistor 3300, an opening reaching the conductor 477 a, an opening reaching the conductor 477 b, and an opening reaching the conductor 477 c. In the openings, the conductor 484 a, the conductor 484 b, the conductor 484 c, and the conductor 484 d are embedded.

The conductor 484 d may have a function of a bottom gate electrode of the transistor 3300. Alternatively, for example, electrical characteristics such as the threshold voltage of the transistor 3300 may be controlled by application of a constant potential to the conductor 484 d. Further alternatively, for example, the conductor 484 d and the top gate electrode of the transistor 3300 may be electrically connected to each other. Thus, the on-state current of the transistor 3300 can be increased. A punch-through phenomenon can be suppressed; thus, stable electric characteristics in the saturation region of the transistor 3300 can be obtained.

In addition, the insulator 402 includes an opening reaching the conductor 484 a, an opening reaching the conductor 484 c, and an opening reaching the conductor 484 b.

The insulator 465 has an opening reaching the conductor 485 a, an opening reaching the conductor 485 b, and an opening reaching the conductor 485 c. In the openings, the conductor 487 a, the conductor 487 b, and the conductor 487 c are embedded.

The conductor 488 a in contact with the conductor 487 a, the conductor 488 b in contact with the conductor 487 b, and the conductor 488 c in contact with the conductor 487 c are provided over the insulator 465. In addition, the insulator 467 includes an opening reaching the conductor 488 a and an opening reaching the conductor 488 b. In the openings, the conductor 490 a and the conductor 490 b are embedded. The conductor 488 c is in contact with the conductor 494 which is one of the electrodes of the capacitor 3400.

The conductor 489 a in contact with the conductor 490 a and the conductor 489 b in contact with the conductor 490 b are provided over the insulator 467. The insulator 469 includes an opening reaching the conductor 489 a, an opening reaching the conductor 489 b, an opening reaching the conductor 496 which is the other of electrodes of the capacitor 3400. In the openings, the conductor 491 a, the conductor 491 b, and the conductor 491 c are embedded.

The conductor 492 a in contact with the conductor 491 a, the conductor 492 b in contact with the conductor 491 b, and the conductor 492 c in contact with the conductor 491 c are provided over the insulator 469.

The insulators 464, 466, 468, 470, 472, 475, 402, 410, 465, 467, 469, and 498 may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator 401 may be formed of, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

The insulator that has a function of blocking oxygen and impurities such as hydrogen is preferably included in at least one of the insulators 464, 466, 468, 470, 472, 475, 402, 410, 465, 467, 469, and 498. When an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistor 3300, the electrical characteristics of the transistor 3300 can be stable.

An insulator having a function of blocking oxygen and impurities such as hydrogen may have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

Each of the conductors 480 a, 480 b, 480 c, 478 a, 478 b, 478 c, 476 a, 476 b, 476 c, 479 a, 479 b, 479 c, 477 a, 477 b, 477 c, 484 a, 484 b, 484 c, 484 d, 483 a, 483 b, 483 c, 483 d, 485 a, 485 b, 485 c, 485 d, 487 a, 487 b, 487 c, 488 a, 488 b, 488 c, 490 a, 490 b, 489 a, 489 b, 491 a, 491 b, 491 c, 492 a, 492 b, 492 c, 494, and 496 may have a single-layer structure or a stacked-layer structure including a conductor containing, for example, one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

An oxide semiconductor is preferably used as the semiconductor 406 b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like can be used in some cases.

As the insulator 406 a and the insulator 406 c, oxides containing one or more, or two or more elements other than oxygen included in the semiconductor 406 b are preferably used. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like can be used in some cases.

The source or drain of the transistor 3200 is electrically connected to the conductor that is one of the source electrode and the drain electrode of the transistor 3300 through the conductor 480 a, the conductor 478 a, the conductor 476 a, the conductor 479 a, the conductor 477 a, the conductor 484 a, the conductor 483 a, and the conductor 485 a. The conductor 454 that is the gate electrode of the transistor 3200 is electrically connected to the conductor that is the other of the source electrode and the drain electrode of the transistor 3300 through the conductor 480 c, the conductor 478 c, the conductor 476 c, the conductor 479 c, the conductor 477 c, the conductor 484 c, the conductor 483 c, and the conductor 485 c.

The capacitor 3400 includes the conductor 494 which is one of the electrodes of the capacitor 3400 and electrically connected to one of the source electrode and the drain electrode of the transistor 3300 through the conductor 483 c, the conductor 485 c, the conductor 487 c, and the conductor 488 c; the insulator 498; and the conductor 496 which is the other electrode of the capacitor 3400. The capacitor 3400 is preferably formed above or below the transistor 3300 because the semiconductor can be reduced in size.

For the structures of other components, the description of FIGS. 1A to 1C and the like can be referred to as appropriate.

A semiconductor device in FIG. 34 is the same as the semiconductor device in FIG. 33 except the structure of the transistor 3200. Therefore, the description of the semiconductor device in FIG. 33 is referred to for the semiconductor device in FIG. 34. Specifically, in the semiconductor device in FIG. 34, the transistor 3200 is a FIN-type transistor. The effective channel width is increased in the FIN-type transistor 3200, whereby the on-state characteristics of the transistor 3200 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 3200 can be improved. Note that the transistor 3200 may be a p-channel transistor or an n-channel transistor.

Although an example in which the transistor 3300 is over the transistor 3200 and the capacitor 3400 is over the transistor 3300 is illustrated in this embodiment, one or more transistors including a semiconductor similar to that included in the transistor 3300 may be provided over the transistor 3200. With such a structure, the degree of integration of the semiconductor device can be further increased.

<Memory Device 2>

The semiconductor device in FIG. 32B is different from the semiconductor device in FIG. 32A in that the transistor 3200 is not provided. Also in this case, data can be written and retained in a manner similar to that of the semiconductor device in FIG. 32A.

Reading of data in the semiconductor device in FIG. 32B is described. When the transistor 3300 is turned on, the third wiring 3003 which is in a floating state and the capacitor 3400 are electrically connected to each other, and the charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 is changed. The amount of change in the potential of the third wiring 3003 varies depending on the potential of the one of the electrode of the capacitor 3400 (or the charge accumulated in the capacitor 3400).

For example, the potential of the third wiring 3003 after the charge redistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potential of the one electrode of the capacitor 3400, C is the capacitance of the capacitor 3400, C_(B) is the capacitance component of the third wiring 3003, and V_(B0) is the potential of the third wiring 3003 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor 3400 is V₁ and V₀ (V₁>V₀), the potential of the third wiring 3003 in the case of retaining the potential V₁ (=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of the third wiring 3003 in the case of retaining the potential V₀ (=(C_(B)×V_(B0)+Cλ V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with a predetermined potential, data can be read.

In this case, a transistor including the first semiconductor may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor may be stacked over the driver circuit as the transistor 3300.

When including a transistor using an oxide semiconductor and having an low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).

Further, in the semiconductor device, high voltage is not needed for writing data and deterioration of elements is less likely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the semiconductor device of one embodiment of the present invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the state of the transistor (on or off), whereby high-speed operation can be easily achieved. At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Embodiment 6 Structure 2 of Semiconductor Device

In this embodiment, an example of a circuit including the transistor of one embodiment of the present invention is described with reference to drawings.

<Cross-Sectional Structure>

FIGS. 35A and 35B are cross-sectional views of a semiconductor device of one embodiment of the present invention. In FIG. 35A, X1-X2 direction represents a channel length direction, and in FIG. 35B, Y1-Y2 direction represents a channel width direction. The semiconductor device illustrated in FIGS. 35A and 35B includes a transistor 2200 containing a first semiconductor material in a lower portion and a transistor 2100 containing a second semiconductor material in an upper portion. In FIGS. 35A and 35B, an example is illustrated in which the transistor illustrated in FIGS. 1A to 1C is used as the transistor 2100 containing the second semiconductor material.

Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (examples of such a semiconductor material include silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor), and the second semiconductor material can be an oxide semiconductor. A transistor containing an oxide semiconductor and described in the above embodiment has excellent subthreshold characteristics and a minute structure. Furthermore, the transistor can operate at a high speed because of its high switching speed and has low leakage current because of its low off-state current.

The transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used in accordance with a circuit. Furthermore, the specific structure of the semiconductor device, such as the material or the structure used for the semiconductor device, is not necessarily limited to those described here except for the use of the transistor of one embodiment of the present invention which contains an oxide semiconductor.

FIGS. 35A and 35B illustrate a structure in which the transistor 2100 is provided over the transistor 2200 with an insulator 2201, an insulator 2207, and an insulator 2208 provided therebetween. A plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. Furthermore, wirings and electrodes provided in the upper layer where the transistor 2100 is provided are electrically connected to wirings and electrodes provided in the lower layer where the transistor 2200 is provided, through a plurality of plugs 2203 embedded in the insulators. An insulator 2204 covering the transistor 2100 and a wiring 2205 over the insulator 2204 are provided.

The stack of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated.

Here, in the case where a silicon-based semiconductor material is used for the transistor 2200 provided in a lower portion, hydrogen in an insulator provided in the vicinity of the semiconductor film of the transistor 2200 terminates dangling bonds of silicon; accordingly, the reliability of the transistor 2200 can be improved. Meanwhile, in the case where an oxide semiconductor is used for the transistor 2100 provided in an upper portion, hydrogen in an insulator provided in the vicinity of the semiconductor film of the transistor 2100 becomes a factor of generating carriers in the oxide semiconductor; thus, the reliability of the transistor 2100 might be decreased. Therefore, in the case where the transistor 2100 using an oxide semiconductor is provided over the transistor 2200 using a silicon-based semiconductor material, it is particularly effective that the insulator 2207 having a function of preventing diffusion of hydrogen is provided between the transistors 2100 and 2200. The insulator 2207 makes hydrogen remain in the lower portion, thereby improving the reliability of the transistor 2200. In addition, since the insulator 2207 suppresses diffusion of hydrogen from the lower portion to the upper portion, the reliability of the transistor 2100 also can be improved.

The insulator 2207 can be, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ).

Furthermore, a blocking film having a function of preventing diffusion of hydrogen is preferably formed over the transistor 2100 to cover the transistor 2100 including an oxide semiconductor film. For the blocking film, a material that is similar to that of the insulator 2207 can be used, and in particular, an aluminum oxide film is preferably used. Using the aluminum oxide film, excess oxygen can be added to the insulator under the aluminum oxide film in the deposition, and the excess oxygen moves to the oxide semiconductor layer of the transistor 2100 by heat treatment, which has an effect of repairing a defect in the oxide semiconductor layer. The aluminum oxide film has a high shielding (blocking) effect of preventing penetration of both oxygen and impurities such as hydrogen and moisture. Thus, by using the aluminum oxide film as the blocking film covering the transistor 2100, release of oxygen from the oxide semiconductor film included in the transistor 2100 and entry of water and hydrogen into the oxide semiconductor film can be prevented. Note that as the block film, the insulator 2204 having a stacked-layer structure may be used, or the block film may be provided under the insulator 2204.

Note that the transistor 2200 can be a transistor of various types without being limited to a planar type transistor. For example, the transistor 2200 can be a fin-type transistor, a tri-gate transistor, or the like. An example of a cross-sectional view in this case is shown in FIGS. 35E and 35F. An insulator 2212 is provided over a semiconductor substrate 2211. The semiconductor substrate 2211 includes a projecting portion with a thin tip (also referred to a fin). Note that an insulator may be provided over the projecting portion. The insulator functions as a mask for preventing the semiconductor substrate 2211 from being etched when the projecting portion is formed. The projecting portion does not necessarily have the thin tip; a projecting portion with a cuboid-like projecting portion and a projecting portion with a thick tip are permitted, for example. A gate insulator 2214 is provided over the projecting portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided over the gate insulator 2214. Source and drain regions 2215 are formed in the semiconductor substrate 2211. Note that here is shown an example in which the semiconductor substrate 2211 includes the projecting portion; however, a semiconductor device of one embodiment of the present invention is not limited thereto. For example, a semiconductor region having a projecting portion may be formed by processing an SOI substrate.

At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Embodiment 7 CMOS Circuit

A circuit diagram in FIG. 35C shows a configuration of what is called a CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and in which gates of them are connected to each other.

[Analog Switch]

A circuit diagram in FIG. 35D shows a configuration in which sources of the transistors 2100 and 2200 are connected to each other and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, the transistors can function as what is called an analog switch. At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Embodiment 8 CPU

A CPU including a semiconductor device such as any of the above-described transistors or the above-described memory device is described below.

FIG. 36 is a block diagram illustrating a configuration example of a CPU including any of the above-described transistors as a component.

The CPU illustrated in FIG. 36 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and an ROM interface 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 36 is just an example of a simplified structure, and an actual CPU may have a variety of structures depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 36 or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 processes an interrupt request from an external input/output device or a peripheral circuit depending on its priority or a mask state. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 depending on the state of the CPU.

In the CPU illustrated in FIG. 36, a memory cell is provided in the register 1196. For the memory cell of the register 1196, any of the above-described transistors, the above-described memory device, or the like can be used.

In the CPU illustrated in FIG. 36, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is held by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data holding by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data holding by the capacitor is selected, the data is rewritten in the capacitor, and supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 37 is an example of a circuit diagram of a memory element that can be used as the register 1196. A memory element 1200 includes a circuit 1201 in which stored data is volatilized when power supply is stopped, a circuit 1202 in which stored data is not volatilized even when power supply is stopped, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a circuit 1220 having a selecting function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include another element such as a diode, a resistor, or an inductor, as needed.

Here, the above-described memory device can be used as the circuit 1202. When supply of a power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 in the circuit 1202 is turned off continues to be input to a gate of the transistor 1209. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213 having one conductivity type (e.g., an n-channel transistor) and the switch 1204 is a transistor 1214 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch 1203 corresponds to one of a source and a drain of the transistor 1213, a second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and conduction or non-conduction between the first terminal and the second terminal of the switch 1203 (i.e., the on/off state of the transistor 1213) is selected by a control signal RD input to a gate of the transistor 1213. A first terminal of the switch 1204 corresponds to one of a source and a drain of the transistor 1214, a second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and conduction or non-conduction between the first terminal and the second terminal of the switch 1204 (i.e., the on/off state of the transistor 1214) is selected by the control signal RD input to a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 1203 (the one of the source and the drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207 are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1207 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1207 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor 1208 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1208 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1208 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line).

The capacitor 1207 and the capacitor 1208 can be omitted when the parasitic capacitance of the transistor, the line, or the like is actively utilized.

A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. As for each of the switch 1203 and the switch 1204, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state.

A signal corresponding to data retained in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 37 illustrates an example in which a signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The logic value of a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is inverted by the logic element 1206, and the inverted signal is input to the circuit 1201 through the circuit 1220.

In the example of FIG. 37, a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without its logic value being inverted. For example, in the case where the circuit 1201 includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) can be input to the node.

In FIG. 37, the transistors included in the memory element 1200 except for the transistor 1209 can each be a transistor in which a channel is formed in a film formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, the transistor can be a transistor whose channel is formed in a silicon film or a silicon substrate. Alternatively, all the transistors in the memory element 1200 may be a transistor in which a channel is formed in an oxide semiconductor. Further alternatively, in the memory element 1200, a transistor in which a channel is formed in an oxide semiconductor can be included besides the transistor 1209, and a transistor in which a channel is formed in a layer including a semiconductor other than an oxide semiconductor or the substrate 1190 can be used for the rest of the transistors.

As the circuit 1201 in FIG. 37, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter or a clocked inverter can be used.

In a period during which the memory element 1200 is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit 1201 by the capacitor 1208 which is provided in the circuit 1202.

The off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor 1209, a signal held in the capacitor 1208 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 1200. The memory element 1200 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.

Since the above-described memory element performs pre-charge operation with the switch 1203 and the switch 1204, the time required for the circuit 1201 to retain original data again after the supply of the power supply voltage is restarted can be shortened.

In the circuit 1202, a signal retained by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after supply of the power supply voltage to the memory element 1200 is restarted, the signal retained by the capacitor 1208 can be converted into the one corresponding to the state (the on state or the off state) of the transistor 1210 to be read from the circuit 1202. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 1208 varies to some degree.

By using the above-described memory element 1200 for a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Further, shortly after the supply of the power supply voltage is restarted, the memory element can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor. Accordingly, power consumption can be suppressed.

Although the memory element 1200 is used in a CPU in this embodiment, the memory element 1200 can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency (RF) tag.

At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Embodiment 9 Imaging Device

FIG. 38A is a top view illustrating an example of an imaging device 200 of one embodiment of the present invention. The imaging device 200 includes a pixel portion 210 and peripheral circuits for driving the pixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290). The pixel portion 210 includes a plurality of pixels 211 arranged in a matrix with p rows and q columns (p and q are each a natural number greater than or equal to 2). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211, and a signal for driving the plurality of pixels 211 is supplied. In this specification and the like, in some cases, “a peripheral circuit” or “a driver circuit” indicates all of the peripheral circuits 260, 270, 280, and 290. For example, the peripheral circuit 260 can be regarded as part of the peripheral circuit.

The imaging device 200 preferably includes a light source 291. The light source 291 can emit detection light P1.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. The peripheral circuit may be formed over a substrate where the pixel portion 210 is formed. Alternatively, a semiconductor device such as an IC chip may be used as part or the whole of the peripheral circuit. Note that one or more of the peripheral circuits 260, 270, 280, and 290 may be omitted.

As illustrated in FIG. 38B, the pixels 211 may be provided to be inclined in the pixel portion 210 included in the imaging device 200. When the pixels 211 are obliquely arranged, the distance between pixels (pitch) can be shortened in the row direction and the column direction. Accordingly, the quality of an image taken with the imaging device 200 can be improved.

<Configuration Example 1 of Pixel>

The pixel 211 included in the imaging device 200 is formed with a plurality of subpixels 212, and each subpixel 212 is combined with a filter which transmits light with a specific wavelength band (color filter), whereby data for achieving color image display can be obtained.

FIG. 39A is a top view showing an example of the pixel 211 with which a color image is obtained. The pixel 211 illustrated in FIG. 39A includes the subpixel 212 provided with a color filter that transmits light with a red (R) wavelength band (also referred to as a subpixel 212R), a subpixel 212 provided with a color filter that transmits light with a green (G) wavelength band (also referred to as a subpixel 212G), and a subpixel 212 provided with a color filter that transmits light with a blue (B) wavelength band (also referred to as a subpixel 212B). The subpixel 212 can function as a photosensor.

The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel 212B) is electrically connected to a wiring 231, a wiring 247, a wiring 248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, the subpixel 212G, and the subpixel 212B are connected to respective wirings 253 which are independent from one another. In this specification and the like, for example, the wiring 248 and the wiring 249 that are connected to the pixel 211 in the n-th row are referred to as a wiring 248[n] and a wiring 249[n], respectively. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253[m]. Note that in FIG. 39A, the wirings 253 connected to the subpixel 212R, the subpixel 212G, and the subpixel 212B in the pixel 211 in the m-th column are referred to as a wiring 253[m]R, a wiring 253[m]G, and a wiring 253[m]B. The subpixels 212 are electrically connected to the peripheral circuit through the above wirings.

The imaging device 200 has a structure in which the subpixel 212 is electrically connected to the subpixel 212 in an adjacent pixel 211 that is provided with a color filter that transmits light with the same wavelength band as the subpixel 212, via a switch. FIG. 39B shows a connection example of the subpixels 212: the subpixel 212 in the pixel 211 arranged in an n-th (n is an integer greater than or equal to 1 and less than or equal to p) row and an m-th (m is an integer greater than or equal to 1 and less than or equal to q) column and the subpixel 212 in the adjacent pixel 211 arranged in an (n+1)-th row and the m-th column. In FIG. 39B, the subpixel 212R arranged in the n-th row and the m-th column and the subpixel 212R arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 201. The subpixel 212G arranged in the n-th row and the m-th column and the subpixel 212G arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 202. The subpixel 212B arranged in the n-th row and the m-th column and the subpixel 212B arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 203.

The color filter used in the subpixel 212 is not limited to red (R), green (G), and blue (B) color filters, and color filters that transmit light of cyan (C), yellow (Y), and magenta (M) may be used. By provision of the subpixels 212 that sense light with three different wavelength bands in one pixel 211, a full-color image can be obtained.

The pixel 211 including the subpixel 212 provided with a color filter transmitting yellow (Y) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting red (R), green (G), and blue (B) light. The pixel 211 including the subpixel 212 provided with a color filter transmitting blue (B) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting cyan (C), yellow (Y), and magenta (M) light. When the subpixels 212 sensing light with four different wavelength bands are provided in one pixel 211, the reproducibility of colors of an obtained image can be increased.

For example, in FIG. 39A, in regard to the subpixel 212 sensing light of a red wavelength band, the subpixel 212 sensing light of a green wavelength band, and the subpixel 212 sensing light of a blue wavelength band, the pixel number ratio (or the light receiving area ratio) thereof is not necessarily 1:1:1. For example, it is possible to employ the Bayer arrangement, in which the ratio of the number of pixels (the ratio of light-receiving areas) is set to red:green:blue=1:2:1. Alternatively, the pixel number ratio (the ratio of light receiving area) of red and green to blue may be 1:6:1.

Although the number of subpixels 212 provided in the pixel 211 may be one, two or more subpixels are preferably provided. For example, when two or more subpixels 212 sensing light of the same wavelength band are provided, the redundancy is increased, and the reliability of the imaging device 200 can be increased.

When an infrared (IR) filter that transmits infrared light and absorbs or reflects visible light is used as the filter, the imaging device 200 that senses infrared light can be achieved.

Furthermore, when a neutral density (ND) filter (dark filter) is used, output saturation which occurs when a large amount of light enters a photoelectric conversion element (light-receiving element) can be prevented. With a combination of ND filters with different dimming capabilities, the dynamic range of the imaging device can be increased.

Besides the above-described filter, the pixel 211 may be provided with a lens. An arrangement example of the pixel 211, a filter 254, and a lens 255 is described with cross-sectional views in FIGS. 40A and 40B. With the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 40A, light 256 enters a photoelectric conversion element 220 through the lens 255, the filter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixel circuit 230, and the like which are provided in the pixel 211.

However, part of the light 256 indicated by arrows might be blocked by some wirings 257 as indicated by a region surrounded with dashed-dotted lines. Thus, a preferable structure is such that the lens 255 and the filter 254 are provided on the photoelectric conversion element 220 side as illustrated in FIG. 40B, whereby the photoelectric conversion element 220 can efficiently receive the light 256. When the light 256 enters the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIGS. 40A and 40B, a photoelectric conversion element in which a p-n junction or a p-i-n junction is formed may be used.

The photoelectric conversion element 220 may be formed using a substance that has a function of absorbing a radiation and generating electric charges. Examples of the substance that has a function of absorbing a radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 can have a light absorption coefficient in a wide wavelength range, such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays.

One pixel 211 included in the imaging device 200 may include the subpixel 212 with a first filter in addition to the subpixel 212 illustrated in FIGS. 40A and 40B.

<Configuration Example 2 of Pixel>

An example of a pixel including a transistor using silicon and a transistor using an oxide semiconductor according to one embodiment of the present invention is described below.

FIGS. 41A and 41B are each a cross-sectional view of an element included in an imaging device.

The imaging device illustrated in FIG. 41A includes a transistor 351 including silicon over a silicon substrate 300, transistors 353 and 354 which include an oxide semiconductor and are stacked over the transistor 351, and a photodiode 360 provided in a silicon substrate 300 and including an anode 361 and a cathode 362. The transistors and the photodiode 360 are electrically connected to various plugs 370 and wirings 371. In addition, an anode 361 of the photodiode 360 is electrically connected to the plug 370 through a low-resistance region 363.

The imaging device includes a layer 305 including the transistor 351 provided on the silicon substrate 300 and the photodiode 360 provided in the silicon substrate 300, a layer 320 which is in contact with the layer 305 and includes the wirings 371, a layer 331 which is in contact with the layer 320 and includes the transistors 353 and 354, and a layer 340 which is in contact with the layer 331 and includes a wiring 372 and a wiring 373.

Note that in the example of cross-sectional view in FIG. 41A, a light-receiving surface of the photodiode 360 is provided on the side opposite to a surface of the silicon substrate 300 where the transistor 351 is formed. With this structure, an optical path can be obtained without the influence by the transistors or wirings, and therefore, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 360 can be the same as the surface where the transistor 351 is formed.

In the case where switching elements for pixels are formed with use of transistors, the layer 305 may include the transistors. Alternatively, the layer 305 may be omitted, in which case pixels may include only transistors.

In addition, in the cross-sectional view in FIG. 41A, the photodiode 360 in the layer 305 and the transistor in the layer 331 can be formed so as to overlap with each other. Thus, the degree of integration of pixels can be increased. In other words, the resolution of the imaging device can be increased.

An imaging device shown in FIG. 41B includes a photodiode 365 in the layer 340 and over the transistor. In FIG. 41B, the layer 305 includes the transistor 351 and a transistor 352 using silicon, the layer 320 includes the wiring 371, the layer 331 includes the transistors 353 and 354 using an oxide semiconductor layer, the layer 340 includes the photodiode 365. The photodiode 365 includes a semiconductor layer 366, a semiconductor layer 367, and a semiconductor layer 368, and is electrically connected to the wiring 373 and a wiring 374 through the plug 370.

The element structure shown in FIG. 41B can increase the aperture ratio.

Alternatively, a PIN diode element formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used as the photodiode 365. In the photodiode 365, an n-type semiconductor layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are stacked in this order. The i-type semiconductor layer 367 is preferably formed using amorphous silicon. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 can each be formed using amorphous silicon, microcrystalline silicon, or the like which includes a dopant imparting the corresponding conductivity type. A photodiode in which the photodiode 365 is formed using amorphous silicon has high sensitivity in a visible light wavelength region, and therefore can easily sense weak visible light.

Here, an insulator 380 is provided between the layer 305 including the transistor 351 and the photodiode 360 and the layer 331 including the transistors 353 and 354. However, there is no limitation on the position of the insulator 380.

Hydrogen in an insulator provided in the vicinity of a channel formation region of the transistor 351 terminates dangling bonds of silicon; accordingly, the reliability of the transistor 351 can be improved. In contrast, hydrogen in the insulator provided in the vicinity of the transistor 353, the transistor 354, and the like becomes one of factors generating a carrier in the oxide semiconductor. Thus, the hydrogen may cause a reduction of the reliability of the transistor 354, the transistor 354, and the like. Therefore, in the case where the transistor using an oxide semiconductor is provided over the transistor using a silicon-based semiconductor, it is preferable that the insulator 380 having a function of blocking hydrogen be provided between the transistors. When the hydrogen is confined below the insulator 380, the reliability of the transistor 351 can be improved. In addition, the hydrogen can be prevented from being diffused from a part below the insulator 380 to a part above the insulator 380; thus, the reliability of the transistor 353, the transistor 354, and the like can be increased.

At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

Embodiment 10 RF Tag

In this embodiment, an RF tag that includes the transistor described in any of the above embodiments or the memory device described in the above embodiment is described with reference to FIG. 42.

The RF tag of this embodiment includes a memory circuit, stores necessary data in the memory circuit, and transmits and receives data to/from the outside by using contactless means, for example, wireless communication. With these features, the RF tag can be used for an individual authentication system in which an object or the like is recognized by reading the individual information, for example. Note that the RF tag is required to have extremely high reliability in order to be used for this purpose.

A configuration of the RF tag will be described with reference to FIG. 42. FIG. 42 is a block diagram illustrating a configuration example of an RF tag.

As shown in FIG. 42, an RF tag 800 includes an antenna 804 which receives a radio signal 803 that is transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. A transistor having a rectifying function included in the demodulation circuit 807 may be formed using a material which enables a reverse current to be low enough, for example, an oxide semiconductor. This can suppress the phenomenon of a rectifying function becoming weaker due to generation of a reverse current and prevent saturation of the output from the demodulation circuit. In other words, the input to the demodulation circuit and the output from the demodulation circuit can have a relation closer to a linear relation. Note that data transmission methods are roughly classified into the following three methods: an electromagnetic coupling method in which a pair of coils is provided so as to face each other and communicates with each other by mutual induction, an electromagnetic induction method in which communication is performed using an induction field, and a radio wave method in which communication is performed using a radio wave. Any of these methods can be used in the RF tag 800 described in this embodiment.

Next, a structure of each circuit will be described. The antenna 804 exchanges the radio signal 803 with the antenna 802 which is connected to the communication device 801. The rectifier circuit 805 generates an input potential by rectification, for example, half-wave voltage doubler rectification of an input alternating signal generated by reception of a radio signal at the antenna 804 and smoothing of the rectified signal with a capacitor provided in a later stage in the rectifier circuit 805. Note that a limiter circuit may be provided on an input side or an output side of the rectifier circuit 805. The limiter circuit controls electric power so that electric power which is higher than or equal to certain electric power is not input to a circuit in a later stage if the amplitude of the input alternating signal is high and an internal generation voltage is high.

The constant voltage circuit 806 generates a stable power supply voltage from an input potential and supplies it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit which generates a reset signal of the logic circuit 809 by utilizing rise of the stable power supply voltage.

The demodulation circuit 807 demodulates the input alternating signal by envelope detection and generates the demodulated signal. Further, the modulation circuit 808 performs modulation in accordance with data to be output from the antenna 804.

The logic circuit 809 analyzes and processes the demodulated signal. The memory circuit 810 holds the input data and includes a row decoder, a column decoder, a memory region, and the like. Further, the ROM 811 stores an identification number (ID) or the like and outputs it in accordance with processing.

Note that the decision whether each circuit described above is provided or not can be made as appropriate as needed.

Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain data even when not powered, the memory circuit can be favorably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention needs power (voltage) needed for data writing significantly lower than that needed in a conventional nonvolatile memory; thus, it is possible to prevent a difference between the maximum communication range in data reading and that in data writing. Furthermore, it is possible to suppress malfunction or incorrect writing which is caused by power shortage in data writing.

Since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be used as the ROM 811. In this case, it is preferable that a manufacturer separately prepare a command for writing data to the ROM 811 so that a user cannot rewrite data freely. Since the manufacturer gives identification numbers before shipment and then starts shipment of products, instead of putting identification numbers to all the manufactured RF tags, it is possible to put identification numbers to only good products to be shipped. Thus, the identification numbers of the shipped products are in series and customer management corresponding to the shipped products is easily performed.

This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification.

Embodiment 11 Display Device

A display device of one embodiment of the present invention is described below with reference to FIGS. 43A to 43C and FIGS. 44A and 44B.

Examples of a display element provided in the display device include a liquid crystal element (also referred to as a liquid crystal display element) and a light-emitting element (also referred to as a light-emitting display element). The light-emitting element includes, in its category, an element whose luminance is controlled by a current or voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. A display device including an EL element (EL display device) and a display device including a liquid crystal element (liquid crystal display device) are described below as examples of the display device.

Note that the display device described below includes in its category a panel in which a display element is sealed and a module in which an IC such as a controller is mounted on the panel.

The display device described below refers to an image display device or a light source (including a lighting device). The display device includes any of the following modules: a module provided with a connector such as an FPC or TCP; a module in which a printed wiring board is provided at the end of TCP; and a module in which an integrated circuit (IC) is mounted directly on a display element by a COG method.

FIGS. 43A to 43C illustrate an example of an EL display device of one embodiment of the present invention. FIG. 43A is a circuit diagram of a pixel in an EL display device. FIG. 43B is a top view showing the whole of the EL display device. FIG. 43C is a cross-sectional view taken along part of dashed-dotted line M-N in FIG. 43B.

FIG. 43A illustrates an example of a circuit diagram of a pixel used in an EL display device.

Note that in this specification and the like, it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all the terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In other words, one embodiment of the invention can be clear even when connection portions are not specified. Further, in the case where a connection portion is disclosed in this specification and the like, it can be determined that one embodiment of the invention in which a connection portion is not specified is disclosed in this specification and the like, in some cases. Particularly in the case where the number of portions to which a terminal is connected might be more than one, it is not necessary to limit the portions to which the terminal is connected to specific portions. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected.

Note that in this specification and the like, it might be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. In other words, when a function of a circuit is specified, one embodiment of the present invention can be clear. Further, it can be determined that one embodiment of the present invention whose function is specified is disclosed in this specification and the like. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted.

The EL display device illustrated in FIG. 43A includes a switching element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.

Note that FIG. 43A and the like each illustrate an example of a circuit structure; therefore, a transistor can be provided additionally. In contrast, for each node in FIG. 43A and the like, it is possible not to provide an additional transistor, switch, passive element, or the like.

A gate of the transistor 741 is electrically connected to one terminal of the switching element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and one electrode of the light-emitting element 719. A power supply potential VDD is supplied to a drain of the transistor 741. The other terminal of the switching element 743 is electrically connected to a signal line 744. A constant potential is supplied to the other electrode of the light-emitting element 719. The constant potential is a ground potential GND or a potential lower than the ground potential GND.

It is preferable to use a transistor as the switching element 743. When the transistor is used as the switching element, the area of a pixel can be reduced, so that the EL display device can have high resolution. As the switching element 743, a transistor formed through the same step as the transistor 741 can be used, so that EL display devices can be manufactured with high productivity. Note that as the transistor 741 and/or the switching element 743, the transistor illustrated in FIGS. 1A to 1C can be used, for example.

FIG. 43B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is provided between the substrate 700 and the substrate 750 so as to surround the pixel 737, the driver circuit 735, and the driver circuit 736. Note that the driver circuit 735 and/or the driver circuit 736 may be provided outside the sealant 734.

FIG. 43C is a cross-sectional view of the EL display device taken along part of dashed-dotted line M-N in FIG. 43B.

FIG. 43C illustrates a structure of the transistor 741 including an insulator 712 over the substrate 700; a conductor 704 a; an insulator 706 a that is over the insulator 712 a and the conductor 704 a and partly overlaps with the conductor 704 a; a semiconductor 706 b over the insulator 706 a; conductors 716 a 1 and 716 a 2 in contact with a top surface of the semiconductor 706 b; an insulator 710 over the conductors 716 a 1 and 716 a 2; an insulator 706 c over the semiconductor 706 b; an insulator 718 b over the insulator 706 c; and a conductor 714 a that is over the insulator 718 b and overlaps with the semiconductor 706 b. Note that the structure of the transistor 741 is just an example; the transistor 741 may have a structure different from that illustrated in FIG. 43C.

In the transistor 741 illustrated in FIG. 43C, the conductor 704 a serves as a gate electrode, the insulator 712 a serves as a gate insulator, the conductor 716 a 1 serves as a source electrode, the conductor 716 a 2 serves as a drain electrode, the insulator 718 b serves as a gate insulator, and the conductor 714 a serves as a gate electrode. Note that in some cases, electrical characteristics of the insulator 706 a, the semiconductor 706 b, and the insulator 706 c change if light enters the insulator 706 a, the semiconductor 706 b, and the insulator 706 c. To prevent this, it is preferable that one or more of the conductor 704 a, the conductor 716 a 1, the conductor 716 a 2, and the conductor 714 a have a light-blocking property.

FIG. 43C illustrates a structure of the capacitor 742 including an insulator 706 d that is over a conductor 704 b and partly overlaps with the conductor 704 b; a semiconductor 706 e over the insulator 706 d; conductors 716 a 3 and 716 a 4 in contact with a top surface of the semiconductor 706 e; the insulator 710 over the conductors 716 a 3 and 716 a 4; an insulator 706 f over the semiconductor 706 e; the insulator 718 b over the insulator 706 f; and a conductor 714 b that is over the insulator 718 b and overlaps with the semiconductor 706 e.

In the capacitor 742, the conductor 704 b serves as one electrode and the conductor 714 b serves as the other electrode.

Thus, the capacitor 742 can be formed using a film of the transistor 741. The conductor 704 a and the conductor 704 b are preferably conductors of the same kind, in which case the conductor 704 a and the conductor 704 b can be formed through the same step. Furthermore, the conductor 714 a and the conductor 714 b are preferably conductors of the same kind, in which case the conductor 714 a and the conductor 714 b can be formed through the same step.

The capacitor 742 illustrated in FIG. 43C has a large capacitance per area occupied by the capacitor. Therefore, the EL display device illustrated in FIG. 43C has high display quality. Note that the structure of the capacitor 742 is just an example and may be different from that illustrated in FIG. 43C.

An insulator 720 is provided over the transistor 741 and the capacitor 742. Here, the insulator 720 may have an opening reaching the conductor 716 a 1 that serves as the source electrode of the transistor 741. A conductor 781 is provided over the insulator 720. The conductor 781 may be electrically connected to the transistor 741 through the opening in the insulator 720.

A partition wall 784 having an opening reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 in contact with the conductor 781 through the opening provided in the partition wall 784 is provided over the partition wall 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light-emitting layer 782, and the conductor 783 overlap with one another serves as the light-emitting element 719.

So far, examples of the EL display device are described. Next, an example of a liquid crystal display device is described.

FIG. 44A is a circuit diagram showing a structural example of a pixel of the liquid crystal display device. A pixel illustrated in FIG. 44A includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 in which a space between a pair of electrodes is filled with a liquid crystal.

One of a source and a drain of the transistor 751 is electrically connected to a signal line 755, and a gate of the transistor 751 is electrically connected to a scan line 754.

One electrode of the capacitor 752 is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode of the capacitor 752 is electrically connected to a wiring for supplying a common potential.

One electrode of the liquid crystal element 753 is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode of the liquid crystal element 753 is electrically connected to a wiring to which a common potential is supplied. The common potential supplied to the wiring electrically connected to the other electrode of the capacitor 752 may be different from that supplied to the other electrode of the liquid crystal element 753.

Note the description of the liquid crystal display device is made on the assumption that the top view of the liquid crystal display device is similar to that of the EL display device. FIG. 44B is a cross-sectional view of the liquid crystal display device taken along dashed-dotted line M-N in FIG. 43B. In FIG. 44B, the FPC 732 is connected to the wiring 733 a via the terminal 731. Note that the wiring 733 a may be formed using the same kind of conductor as the conductor of the transistor 751 or using the same kind of semiconductor as the semiconductor of the transistor 751.

For the transistor 751, the description of the transistor 741 is referred to. For the capacitor 752, the description of the capacitor 742 is referred to. Note that the structure of the capacitor 752 in FIG. 44B corresponds to, but is not limited to, the structure of the capacitor 742 in FIG. 43C.

Note that in the case where an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current of the transistor 751 can be extremely small. Therefore, an electric charge held in the capacitor 752 is unlikely to leak, so that the voltage applied to the liquid crystal element 753 can be maintained for a long time. Accordingly, the transistor 751 can be kept off during a period in which moving images with few motions or a still image are/is displayed, whereby power for the operation of the transistor 751 can be saved in that period; accordingly a liquid crystal display device with low power consumption can be provided. Furthermore, the area occupied by the capacitor 752 can be reduced; thus, a liquid crystal display device with a high aperture ratio or a high-resolution liquid crystal display device can be provided.

An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening portion reaching the transistor 751. A conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening portion in the insulator 721.

An insulator 792 serving as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 serving as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.

Owing to the above-described structure, a display device including a capacitor occupying a small area, a display device with high display quality, or a high-resolution display device can be provided.

For example, in this specification and the like, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ various modes or can include various elements. For example, the display element, the display device, the light-emitting element, or the light-emitting device includes at least one of the following: a light-emitting diode (LED) for white, red, green, or blue color, a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element including a carbon nanotube, and the like. Other than the above, display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect may be included.

Note that examples of display devices having EL elements include an EL display. Examples of a display device including an electron emitter include a field emission display (FED), an SED-type flat panel display (SED: surface-conduction electron-emitter display), and the like. Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display devices having electronic ink or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.

Note that in the case of using an LED, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. As described above, provision of graphene or graphite enables easy formation of a nitride semiconductor thereover, such as an n-type GaN semiconductor including crystals. Furthermore, a p-type GaN semiconductor including crystals or the like can be provided thereover, and thus the LED can be formed. Note that an AlN layer may be provided between the n-type GaN semiconductor including crystals and graphene or graphite. The GaN semiconductors included in the LED may be formed by MOCVD. Note that when the graphene is provided, the GaN semiconductors included in the LED can also be formed by a sputtering method.

Note that in this specification and the like, a transistor can be formed using any of a variety of substrates, for example. The type of a substrate is not limited to a certain type. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, an attachment film, paper including a fibrous material, a base film, and the like. Examples of a glass substrate include a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, and soda lime glass substrate. Examples of the flexible substrate, the attachment film, the base film, and the like are substrates of plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Furthermore, polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride can be given as examples. Other examples are polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, paper, and the like. Specifically, the use of semiconductor substrates, single crystal substrates, SOI substrates, or the like enables the manufacture of small-sized transistors with a small variation in characteristics, size, shape, or the like and with high current capability. A circuit using such transistors achieves lower power consumption of the circuit or higher integration of the circuit.

Alternatively, a flexible substrate may be used as the substrate, and the transistor may be provided directly over the flexible substrate. Further alternatively, a separation layer may be provided between the substrate and the transistor. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate and transferred onto another substrate. In such a case, the transistor can be transferred to a substrate having low heat resistance or a flexible substrate as well. For the above separation layer, a stack including inorganic films, which are a tungsten film and a silicon oxide film, or an organic resin film of polyimide or the like formed over a substrate can be used, for example.

In other words, a transistor may be formed using one substrate, and then transferred to another substrate. Examples of a substrate to which a transistor is transferred include, in addition to the above substrate over which the transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupra, rayon, or regenerated polyester), and the like), a leather substrate, and a rubber substrate. When such a substrate is used, a transistor with excellent properties or a transistor with low power consumption can be formed, a device with high durability, high heat resistance can be provided, or reduction in weight or thickness can be achieved.

This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification.

Embodiment 12

In this embodiment, a display module using a semiconductor device of one embodiment of the present invention is described with reference to FIG. 45.

<Display Module>

In a display module 6000 in FIG. 45, a touch panel 6004 connected to an FPC 6003, a display panel 6006 connected to an FPC 6005, a backlight unit 6007, a frame 6009, a printed board 6010, and a battery 6011 are provided between an upper cover 6001 and a lower cover 6002. Note that the backlight unit 6007, the battery 6011, the touch panel 6004, and the like are not provided in some cases.

The semiconductor device of one embodiment of the present invention can be used for, for example, the display panel 6006 and an integrated circuit mounted on a printed circuit board.

The shapes and sizes of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch panel 6004 and the display panel 6006.

The touch panel 6004 can be a resistive touch panel or a capacitive touch panel and may be formed to overlap with the display panel 6006. A counter substrate (sealing substrate) of the display panel 6006 can have a touch panel function. A photosensor may be provided in each pixel of the display panel 6006 so that an optical touch panel function is added. An electrode for a touch sensor may be provided in each pixel of the display panel 6006 so that a capacitive touch panel function is added.

The backlight unit 6007 includes a light source 6008. The light source 6008 may be provided at an end portion of the backlight unit 6007 and a light diffusing plate may be used.

The frame 6009 protects the display panel 6006 and also functions as an electromagnetic shield for blocking electromagnetic waves generated from the printed board 6010. The frame 6009 may function as a radiator plate.

The printed board 6010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the battery 6011 provided separately may be used. Note that the battery 6011 is not necessary in the case where a commercial power source is used.

The display module 6000 can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification.

Embodiment 13 Package Using a Lead Frame Interposer

FIG. 46A is a perspective view illustrating a cross-sectional structure of a package using a lead frame interposer. In the package illustrated in FIG. 46A, a chip 551 corresponding to the semiconductor device of one embodiment of the present invention is connected to terminals 552 over an interposer 550 by wire bonding. The terminals 552 are placed on a surface of the interposer 550 on which the chip 551 is mounted. The chip 551 may be sealed by a mold resin 553, in which case the chip 551 is sealed such that part of each of the terminals 552 is exposed.

FIG. 46B illustrates the structure of a module of an electronic device (mobile phone) in which a package is mounted on a circuit board. In the module of the mobile phone in FIG. 46B, a package 602 and a battery 604 are mounted on a printed wiring board 601. The printed wiring board 601 is mounted on a panel 600 including a display element by an FPC 603.

This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification.

Embodiment 14

In this embodiment, electronic devices and lighting devices of one embodiment of the present invention will be described with reference to drawings.

<Electronic Device>

Electronic devices and lighting devices can be fabricated using the semiconductor device of one embodiment of the present invention. In addition, highly reliable electronic devices and lighting devices can be fabricated using the semiconductor device of one embodiment of the present invention. Furthermore, electronic devices and lighting devices including touch sensors with improved detection sensitivity can be fabricated using the semiconductor device of one embodiment of the present invention.

Examples of electronic devices include a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone device), a portable game machine, a portable information terminal, an audio reproducing device, a large game machine such as a pinball machine, and the like.

In the case of having flexibility, the electronic device or lighting device of one embodiment of the present invention can be incorporated along a curved inside/outside wall surface of a house or a building or a curved interior/exterior surface of a car.

Furthermore, the electronic device of one embodiment of the present invention may include a secondary battery. It is preferable that the secondary battery be capable of being charged by non-contact power transmission.

As examples of the secondary battery, a lithium ion secondary battery such as a lithium polymer battery (lithium ion polymer battery) using a gel electrolyte, a lithium ion battery, a nickel-hydride battery, a nickel-cadmium battery, an organic radical battery, a lead-acid battery, an air secondary battery, a nickel-zinc battery, and a silver-zinc battery can be given.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display an image, data, or the like on a display portion. When the electronic device includes a secondary battery, the antenna may be used for contactless power transmission.

FIG. 47A illustrates a portable game machine including a housing 7101, a housing 7102, a display portion 7103, a display portion 7104, a microphone 7105, speakers 7106, an operation key 7107, a stylus 7108, and the like. The semiconductor device of one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the housing 7101. When the light-emitting device according of one embodiment of the present invention is used as the display portion 7103 or 7104, it is possible to provide a user-friendly portable game machine with quality that hardly deteriorates. Although the portable game machine illustrated in FIG. 47A includes two display portions, the display portion 7103 and the display portion 7104, the number of display portions included in the portable game machine is not limited to two.

FIG. 47B illustrates a smart watch, which includes a housing 7302, a display portion 7304, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like. The semiconductor device of one embodiment of the present invention can be used for a memory, a CPU, or the like incorporated in the housing 7302.

FIG. 47C illustrates a portable information terminal, which includes a display portion 7502 incorporated in a housing 7501, operation buttons 7503, an external connection port 7504, a speaker 7505, a microphone 7506, and the like. The semiconductor device of one embodiment of the present invention can be used for a mobile memory, a CPU, or the like incorporated in the housing 7501. Note that the display portion 7502 is small- or medium-sized but can perform full high vision, 4 k, or 8 k display because it has significantly high definition; therefore, a significantly clear image can be obtained.

FIG. 47D illustrates a video camera, which includes a first housing 7701, a second housing 7702, a display portion 7703, operation keys 7704, a lens 7705, a joint 7706, and the like. The operation keys 7704 and the lens 7705 are provided for the first housing 7701, and the display portion 7703 is provided for the second housing 7702. The first housing 7701 and the second housing 7702 are connected to each other with the joint 7706, and the angle between the first housing 7701 and the second housing 7702 can be changed with the joint 7706. Images displayed on the display portion 7703 may be switched in accordance with the angle at the joint 7706 between the first housing 7701 and the second housing 7702. The imaging device in one embodiment of the present invention can be provided in a focus position of the lens 7705. The semiconductor device of one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the first housing 7701.

FIG. 47E illustrates a digital signage including a display portion 7922 provided on a utility pole 7921. The display device of one embodiment of the present invention can be used for a control circuit of the display portion 7922.

FIG. 48A illustrates a notebook personal computer, which includes a housing 8121, a display portion 8122, a keyboard 8123, a pointing device 8124, and the like. The semiconductor device of one embodiment of the present invention can be used for a CPU, a memory, or the like incorporated in the housing 8121. Note that the display portion 8122 is small- or medium-sized but can perform 8 k display because it has significantly high definition; therefore, a significantly clear image can be obtained.

FIG. 48B is an external view of an automobile 9700. FIG. 48C illustrates a driver's seat of the automobile 9700. The automobile 9700 includes a car body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like. The semiconductor device of one embodiment of the present invention can be used in a display portion and a control integrated circuit of the automobile 9700. For example, the semiconductor device of one embodiment of the present invention can be used in display portions 9710 to 9715 illustrated in FIG. 48C.

The display portion 9710 and the display portion 9711 are display devices or input/output devices provided in an automobile windshield. The display device or input/output device of one embodiment of the present invention can be a see-through display device or input/output device, through which the opposite side can be seen, by using a light-transmitting conductive material for its electrodes. Such a see-through display device or input/output device does not hinder driver's vision during the driving of the automobile 9700. Therefore, the display device or input/output device of one embodiment of the present invention can be provided in the windshield of the automobile 9700. Note that in the case where a transistor or the like for driving the display device or input/output device is provided in the display device or input/output device, a transistor having light-transmitting properties, such as an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor, is preferably used.

The display portion 9712 is a display device provided on a pillar portion. For example, an image taken by an imaging unit provided in the car body is displayed on the display portion 9712, whereby the view hindered by the pillar portion can be compensated. The display portion 9713 is a display device provided on the dashboard. For example, an image taken by an imaging unit provided in the car body is displayed on the display portion 9713, whereby the view hindered by the dashboard can be compensated. That is, by displaying an image taken by an imaging unit provided on the outside of the automobile, blind areas can be eliminated and safety can be increased. Displaying an image to compensate for the area which a driver cannot see, makes it possible for the driver to confirm safety easily and comfortably.

FIG. 48D illustrates the inside of a car in which a bench seat is used as a driver seat and a front passenger seat. A display portion 9721 is a display device or input/output device provided in a door portion. For example, an image taken by an imaging unit provided in the car body is displayed on the display portion 9721, whereby the view hindered by the door can be compensated. A display portion 9722 is a display device provided in a steering wheel. A display portion 9723 is a display device provided in the middle of a seating face of the bench seat. Note that the display device can be used as a seat heater by providing the display device on the seating face or backrest and by using heat generation of the display device as a heat source.

The display portion 9714, the display portion 9715, and the display portion 9722 can display a variety of kinds of information such as navigation data, a speedometer, a tachometer, a mileage, a fuel meter, a gearshift indicator, and air-condition setting. The content, layout, or the like of the display on the display portions can be changed freely by a user as appropriate. The information listed above can also be displayed on the display portions 9710 to 9713, 9721, and 9723. The display portions 9710 to 9715 and 9721 to 9723 can also be used as lighting devices. The display portions 9710 to 9715 and 9721 to 9723 can also be used as heating devices.

FIG. 49A illustrates an external view of a camera 8000. The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, a connection portion 8005, and the like. A lens 8006 can be put on the camera 8000.

The connection portion 8005 includes an electrode to connect with a finder 8100, which is described below, a stroboscope, or the like.

Although the lens 8006 of the camera 8000 here is detachable from the housing 8001 for replacement, the lens 8006 may be included in a housing.

Images can be taken at the touch of the shutter button 8004. In addition, images can be taken at the touch of the display portion 8002 which serves as a touch panel.

The display device or input/output device of one embodiment of the present invention can be used in the display portion 8002.

FIG. 49B shows the camera 8000 with the finder 8100 connected.

The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 includes a connection portion for the camera 8000 and the connection portion 8005, and the finder 8100 can be connected to the camera 8000. The connection portion includes an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102.

The button 8103 has a function of a power button, and the display portion 8102 can be turned on and off with the button 8103.

The semiconductor device of one embodiment of the present invention can be used for an integrated circuit and an image sensor included in the housing 8101.

Although the camera 8000 and the finder 8100 are separate and detachable electronic devices in FIGS. 49A and 49B, the housing 8001 of the camera 8000 may include a finder having the display device or input/output device of one embodiment of the present invention.

FIG. 49C illustrates an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. The mounting portion 8201 includes a battery 8206.

Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion 8204. In addition, the movement of the eyeball and the eyelid of a user can be captured by a camera in the main body 8203 and then coordinates of the points the user looks at can be calculated using the captured data to utilize the eye of the user as an input means.

The mounting portion 8201 may include a plurality of electrodes to be in contact with the user. The main body 8203 may be configured to sense current flowing through the electrodes with the movement of the user's eyeball to recognize the direction of his or her eyes. The main body 8203 may be configured to sense current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor so that the user's biological information can be displayed on the display portion 8204. The main body 8203 may be configured to sense the movement of the user's head or the like to move an image displayed on the display portion 8204 in synchronization with the movement of the user's head or the like.

The semiconductor device of one embodiment of the present invention can be used for an integrated circuit included in the main body 8203.

At least part of this embodiment can be implemented in combination with any of the embodiments described in this specification as appropriate.

Embodiment 15

In this embodiment, application examples of an RF tag using the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 50A to 50F.

<Application Examples of RF Tag>

The RF tag is widely used and can be provided for, for example, products such as bills, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident's cards, see FIG. 50A), vehicles (e.g., bicycles, see FIG. 50B), packaging containers (e.g., wrapping paper or bottles, see FIG. 50C), recording media (e.g., DVD or video tapes, see FIG. 50D), personal belongings (e.g., bags or glasses), foods, plants, animals, human bodies, clothing, household goods, medical supplies such as medicine and chemicals, and electronic devices (e.g., liquid crystal display devices, EL display devices, television sets, or cellular phones), or tags on products (see FIGS. 50E and 50F).

An RF tag 4000 of one embodiment of the present invention is fixed to a product by being attached to a surface thereof or embedded therein. For example, the RF tag 4000 is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag 4000 of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RF tag 4000 of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag of one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic devices, or the like. Vehicles can also have higher security against theft or the like by being provided with the RF tag of one embodiment of the present invention.

As described above, by using the RF tag including the semiconductor device of one embodiment of the present invention for each application described in this embodiment, power for operation such as writing or reading of data can be reduced, which results in an increase in the maximum communication distance. Moreover, data can be held for an extremely long period even in the state where power is not supplied; thus, the RF tag can be preferably used for application in which data is not frequently written or read.

This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification.

Example 1

In this example, a change in the concentration of carbon in an oxide semiconductor caused by high-density plasma treatment was examined. The results are described below.

Samples were each formed by the following method. A 100-nm-thick silicon oxide was formed on a silicon substrate by a thermal oxidation method, and then a 100-nm-thick In—Ga—Zn oxide film was deposited with a sputtering apparatus using an In—Ga—Zn oxide (with an atomic ratio of In:Ga:Zn=1:1:1) target. The In—Ga—Zn oxide film was deposited under the following conditions: an atmosphere containing an argon gas at 30 sccm and an oxygen gas at 15 sccm was used, the pressure was adjusted to 0.4 Pa, the substrate temperature was set at 300° C., and a power of 0.5 kW was applied from a DC power source to the target.

Next, high-density plasma treatment was performed on the In—Ga—Zn oxide film. The conditions of the high-density plasma treatment for Sample 2 were as follows: an atmosphere containing an argon gas at 900 sccm and an oxygen gas at 5 sccm was used, the pressure was adjusted to 106.67 Pa, the substrate temperature was set at 400° C., and a power of 3800 W (2.45 GHz) was applied for 5 minutes. The conditions of the high-density plasma treatment for Sample 3 were as follows: an atmosphere containing an argon gas at 120 sccm and an oxygen gas at 40 sccm was used, the pressure was adjusted to 666.65 Pa, the substrate temperature was set at 400° C., and a power of 4000 W (2.45 GHz) was applied for 5 minutes. For reference, a sample on which high-density plasma treatment was not performed (Sample 1) was prepared.

The results of secondary ion mass spectrometry (SIMS) performed on the samples formed in the above-described manner are shown in FIG. 51. In FIG. 51, a thick line represents Sample 1, a thin line represents Sample 2, a broken line represents Sample 3, and a dashed-dotted line represents the carbon concentration (2.9×10¹⁸ atoms/cm³) in the background (referred to as “B.G.”).

From the results in FIG. 51, it was found that the carbon concentrations in the oxide semiconductor films of Sample 2 and Sample 3, each of which had been subjected to the high-density plasma treatment, were lower than that of Sample 1, which had not been subjected to high-density plasma treatment. In particular, the carbon concentration in Sample 3, which had been subjected to the high-density plasma treatment under high pressure, was below the concentration in the background and much lower than those in Sample 1 and Sample 2.

Example 2

In this example, degassing of an oxide semiconductor subjected to high-density plasma treatment was examined using thermal desorption spectroscopy (TDS).

Samples were each formed by the following method. A 100-nm-thick silicon oxide was formed on a silicon substrate by a thermal oxidation method, and then a 100-nm-thick In—Ga—Zn oxide film was deposited with a sputtering apparatus using an In—Ga—Zn oxide (with an atomic ratio of In:Ga:Zn=1:1:1) target. The In—Ga—Zn oxide film was deposited under the following conditions: an atmosphere containing an argon gas at 30 sccm and an oxygen gas at 15 sccm was used, the pressure was adjusted to 0.4 Pa, the substrate temperature was set at 300° C., and a power of 0.5 kW was applied from a DC power source to the target.

Next, high-density plasma treatment was performed on the In—Ga—Zn oxide film. The conditions of the high-density plasma treatment for Sample 6 were as follows: an atmosphere containing an argon gas at 120 sccm and an oxygen gas at 40 sccm was used, the pressure was adjusted to 666.65 Pa, the substrate temperature was set at 400° C., and a power of 4000 W (2.45 GHz) was applied for 60 minutes. The conditions of the high-density plasma treatment for Sample 7 were as follows: an atmosphere containing an argon gas at 900 sccm and an oxygen gas at 40 sccm was used, the pressure was adjusted to 666.65 Pa, the substrate temperature was set at 400° C., and a power of 4000 W (2.45 GHz) was applied for 60 minutes. For reference, a sample on which high-density plasma treatment was not performed (Sample 4) was prepared. Further, for reference, a sample which was held for 60 minutes in an atmosphere containing an argon gas at 120 sccm and an oxygen gas at 40 sccm at a pressure of 666.65 Pa and a substrate temperature of 400° C. (Sample 5) was prepared.

Note that the high-density plasma treatment was performed for 60 minutes, where a cycle consisting of 10-minute treatment and a 1-minute interruption of power supply was repeated 6 times. Thus, the load on a power source of the high-density plasma treatment apparatus can be reduced.

FIG. 52 shows TDS results on Samples 4 to 7. Here, the results concerning gases with a m/z of 2 (e.g., H₂), 28 (e.g., N₂), 32 (e.g., O₂), and 44 (e.g., CO₂, C₃H₈) are shown.

According to FIG. 52, the amounts of gas with a m/z of 2 released from Sample 6 and Sample 7, each of which had been subjected to the high-density plasma treatment, were smaller than those released from Sample 4 and Sample 5. Furthermore, the amounts of gas with a m/z of 28 released from Sample 6 and Sample 7, each of which had been subjected to the high-density plasma treatment, were smaller than those released from Sample 4 and Sample 5. Moreover, the amounts of gas with a m/z of 32 released from Sample 6 and Sample 7, each of which had been subjected to the high-density plasma treatment, were larger than those released from Sample 4 and Sample 5. Furthermore, the amounts of gas with a m/z of 44 released at low temperatures from Sample 6 and Sample 7, each of which had been subjected to the high-density plasma treatment, were larger than those released from Sample 4 and Sample 5.

That is, by performing the high-density plasma treatment on the In—Ga—Zn oxide film, hydrogen and nitrogen were reduced, carbon was easily released, and excess oxygen was increased.

For example, hydrogen and nitrogen in the In—Ga—Zn oxide film serve as impurities and are the cause for an increase in carrier density, in some cases. Furthermore, excess oxygen has an effect of reducing the density of defect states in the In—Ga—Zn oxide film. Since the amounts of hydrogen and nitrogen can be reduced by the high-density plasma treatment, the reliability and the like of a transistor including such an In—Ga—Zn oxide film can be improved.

The increase in the amount of gas containing carbon released from the In—Ga—Zn oxide film shows that carbon is easily released by later heat treatment (e.g., annealing). For example, Example 1 shows that the carbon concentration in an In—Ga—Zn oxide film is reduced by high-density plasma treatment, and this reduction in carbon concentration highly possibly occurred because the high-density plasma treatment makes it easier to release carbon from the In—Ga—Zn oxide film. By performing heat treatment after the high-density plasma treatment, the carbon concentration can be further reduced in some cases. In contrast, in Sample 4 and Sample 5, which were not subjected to high-density plasma treatment, the release of carbon hardly occurred during the TDS; this shows that the carbon concentration in the In—Ga—Zn oxide film is difficult to reduce only by simple heat treatment.

Therefore, the high-density plasma treatment has an effect of breaking a weak bond in the oxide semiconductor and reducing impurities such as hydrogen, nitrogen, and carbon.

Example 3

In this example, in order to examine how high-density plasma treatment in an oxygen atmosphere influences an In—Ga—Zn oxide film, a change in states in the energy gap of the In—Ga—Zn oxide film was evaluated by hard X-ray photoelectron spectroscopy (HX-PES).

Samples were each formed by the following method. A 100-nm-thick In—Ga—Zn oxide film was deposited on a silicon substrate with a sputtering apparatus using an In—Ga—Zn oxide (with an atomic ratio of In:Ga:Zn=1:1:1) target. The In—Ga—Zn oxide film was deposited under the following conditions: an atmosphere containing an argon gas at 20 sccm and an oxygen gas at 10 sccm was used, the pressure was adjusted to 0.4 Pa, the substrate temperature was set at 300° C., and a power of 200 W was applied from a DC power source to the target.

Next, high-density plasma treatment was performed on the deposited In—Ga—Zn oxide film. The conditions of the high-density plasma treatment were as follows: an atmosphere containing an argon gas at 900 sccm and an oxygen gas at 40 sccm was used, the pressure was adjusted to 666.65 Pa, the substrate temperature was set at 400° C., and a power of 4000 W (2.45 GHz) was applied for 60 minutes. For reference, a sample on which high-density plasma treatment was not performed was prepared.

Note that the high-density plasma treatment was performed for 60 minutes, where a cycle consisting of 10-minute treatment and a 1-minute interruption of power supply was repeated 6 times. Thus, the load on a power source of the high-density plasma treatment apparatus can be reduced.

FIG. 53A shows the results of HX-PES on the formed samples. In FIG. 53A, the horizontal axis represents binding energy and the vertical axis represents the intensity of a signal (arbitrary unit).

It was found from FIG. 53A that the sample which had been subjected to the high-density plasma treatment had lower binding energy at the valence band maximum than the sample which had not been subjected to high-density plasma treatment by approximately 0.4 eV. The binding energy in the HX-PES results represents the level of energy when the Fermi level is assumed to be 0 eV. Further, by spectroscopic ellipsometry, the samples used here were confirmed to have the same bandgap. Accordingly, the reduction in binding energy indicates a reduction in the Fermi level (a change toward an intrinsic film).

These results show that the high-density plasma treatment on the In—Ga—Zn oxide film lowers the Fermi level of the In—Ga—Zn oxide film (makes the In—Ga—Zn oxide film change toward an intrinsic film).

Moreover, for easy comparison of the difference in deep defect states between the samples, the spectrum shown in FIG. 53A was shifted by the different amount of the Fermi level so that the valence band edges were aligned. The obtained spectra are shown in FIG. 53B.

As indicated by an arrow in FIG. 53B, deep defect states in the In—Ga—Zn oxide film were reduced by performing the high-density plasma treatment on the In—Ga—Zn oxide film.

This application is based on Japanese Patent Application serial no. 2015-052820 filed with Japan Patent Office on Mar. 17, 2015 and Japanese Patent Application serial no. 2015-120925 filed with Japan Patent Office on Jun. 16, 2015, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first insulator over a substrate; a second insulator over the first insulator; a semiconductor over the second insulator; a first conductor and a second conductor over the semiconductor; a third insulator over the semiconductor; a fourth insulator over the third insulator; a third conductor over the fourth insulator; and a fifth insulator over the first insulator, the first conductor and the second conductor, wherein the second insulator and the third insulator each comprise at least one element other than oxygen included in the semiconductor, and wherein the semiconductor comprises a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower.
 2. The semiconductor device according to claim 1, wherein the third insulator has a stacked structure comprising two or more layers.
 3. The semiconductor device according to claim 1, wherein the first conductor, the second conductor and the third conductor each have a stacked structure comprising two or more layers.
 4. The semiconductor device according to claim 1, further comprising a fourth conductor between the substrate and the first insulator.
 5. The semiconductor device according to claim 1, wherein the second insulator comprises a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower.
 6. The semiconductor device according to claim 1, wherein the third insulator comprises a region having a carbon concentration of 3×10¹⁸ atoms/cm³ or lower.
 7. The semiconductor device according to claim 1, wherein the semiconductor comprises a CAAC-OS.
 8. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer; forming a second insulating layer over the first insulating layer; forming a semiconductor layer over the second insulating layer; processing part of the second insulating layer and part of the semiconductor layer to form a multilayer film comprising a first insulating film and a semiconductor film; forming a first conductive layer over the multilayer film; processing part of the first conductive layer to form a first conductive film; forming a third insulating layer over the first conductive film and the first insulating layer; forming a first opening through which the semiconductor film and the first insulating layer are exposed, in the third insulating layer and the first conductive film, to divide the first conductive film into a second conductive film and a third conductive film; forming a fourth insulating layer over the third insulating layer, the second conductive film, the third conductive film and the semiconductor film; forming a fifth insulating layer over the fourth insulating layer; and forming a second conductive layer over the fifth insulating layer, wherein the first insulating film and the fourth insulating layer each comprise at least one element other than oxygen included in the semiconductor film.
 9. The method for manufacturing a semiconductor device, according to claim 8, further comprising the step of performing high-density plasma treatment after the first insulating layer is formed.
 10. The method for manufacturing a semiconductor device, according to claim 8, further comprising the step of performing high-density plasma treatment after the multilayer film is formed.
 11. The method for manufacturing a semiconductor device, according to claim 8, further comprising the step of performing high-density plasma treatment after the first opening is formed in the third insulating layer and the first conductive film.
 12. The method for manufacturing a semiconductor device, according to claim 8, further comprising the step of performing high-density plasma treatment after the fourth insulating layer is formed.
 13. The method for manufacturing a semiconductor device, according to claim 8, further comprising the steps of: processing the second conductive layer to form a fourth conductive film; forming a second opening and a third opening in the third insulating layer through which part of the second conductive film and part of the third conductive film are exposed; and performing high-density plasma treatment after the second opening and the third opening are formed.
 14. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer; forming a second insulating layer over the first insulating layer; forming a semiconductor layer over the second insulating layer; forming a first conductive layer over the semiconductor layer; processing part of the second insulating layer, part of the semiconductor layer and part of the first conductive layer to form a multilayer film comprising a first insulating film, a semiconductor film and a first conductive film; forming a third insulating layer over the multilayer film; forming a first opening through which the semiconductor film is exposed, in the third insulating layer and the first conductive film, to divide the first conductive film into a second conductive film and a third conductive film; forming a fourth insulating layer over the third insulating layer, the second conductive film, the third conductive film and the semiconductor film; forming a fifth insulating layer over the fourth insulating layer; and forming a second conductive layer over the fifth insulating layer, wherein the first insulating film and the fourth insulating layer each comprise at least one element other than oxygen included in the semiconductor layer.
 15. The method for manufacturing a semiconductor device, according to claim 14, further comprising the step of performing high-density plasma treatment after the first insulating layer is formed.
 16. The method for manufacturing a semiconductor device, according to claim 14, further comprising the step of performing high-density plasma treatment after the first opening is formed in the third insulating layer and the first conductive film.
 17. The method for manufacturing a semiconductor device, according to claim 14, further comprising the step of performing high-density plasma treatment after the fifth insulating layer is formed.
 18. The method for manufacturing a semiconductor device, according to claim 14, further comprising the steps of: processing the second conductive layer to form a fourth conductive film; forming a second opening and a third opening in the third insulating layer through which part of the second conductive film and part of the third conductive film are exposed; and performing high-density plasma treatment after the second opening and the third opening are formed.
 19. The method for manufacturing a semiconductor device, according to claim 10, wherein the high-density plasma treatment is performed with a high-frequency generator that generates a wave having a frequency of more than or equal to 0.3 GHz and less than or equal to 3.0 GHz.
 20. The method for manufacturing a semiconductor device, according to claim 10, wherein the high-density plasma treatment is performed in an oxygen atmosphere.
 21. The method for manufacturing a semiconductor device, according to claim 10, wherein the high-density plasma treatment is performed in a nitrogen atmosphere.
 22. The method for manufacturing a semiconductor device, according to claim 10, wherein the high-density plasma treatment is performed while a substrate bias is applied.
 23. The method for manufacturing a semiconductor device, according to claim 10, wherein annealing treatment is performed following the high-density plasma treatment.
 24. The method for manufacturing a semiconductor device, according to claim 10, wherein the high-density plasma treatment is performed following annealing treatment.
 25. The method for manufacturing a semiconductor device, according to claim 8, wherein at least one of the first insulating layer and the third insulating layer is formed using a tetraethoxysilane gas. 